Floorplanning Method For Reducing Thermally-Induced Structural Stress In Chiplet Packages (Penn State, Intel, ASU et al.)


A new technical paper titled "STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration" was published by researchers at Pennsylvania State University, Intel, Arizona State University and University of Notre Dame. Abstract "Chiplet-based architectures and advanced packaging has emerged as transformative approaches in semiconductor design. While conventional ph... » read more

Speeding Up Die-To-Die Interconnectivity


Disaggregating SoCs, coupled with the need to process more data faster, is forcing engineering teams to rethink the electronic plumbing in a system. Wires don't shrink, and just cramming more wires or thicker wires into a package are not viable solutions. Kevin Donnelly, vice president of strategic marketing at Eliyan, talks about how to speed up data movement between chiplets with bi-direction... » read more

Optimizing End-to-End Communication And Workload Partitioning In MCM Accelerators (Georgia Tech)


A new technical paper titled "MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules" was published by researchers at Georgia Tech. Abstract "Increasing AI computing demands and slowing transistor scaling have led to the advent of Multi-Chip-Module (MCMs) based accelerators. MCMs enable cost-effective scalability, higher yield, and modular reuse by par... » read more

On-Chiplet Framework for Verifying Physical Security and Integrity of Adjacent Chiplets


A new technical paper titled "ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification" was published by researchers at Worcester Polytechnic Institute. Abstract "The increasing complexity and cost of manufacturing monolithic chips have driven the semiconductor industry toward chiplet-based designs, where smaller and modular chiplets are integrated onto a singl... » read more

Challenges of Chiplet Placement And Routing Optimization (KAIST)


A new technical paper titled "Advanced Chiplet Placement and Routing Optimization considering Signal Integrity" was published by researchers at KAIST. Abstract: "This article addresses the critical challenges of chiplet placement and routing optimization in the era of advanced packaging and heterogeneous integration. We present a novel approach that formulates the problem as a signal integr... » read more

Can Chiplets Serve Cost-Conscious Apps?


Chiplets are emerging as a significant new phase in the evolution of the semiconductor market, providing a way to continue scaling performance well beyond the size limitations of a reticle. But that improvement comes with a high price tag and a lot more complexity, which so far has limited adoption. One of the main reasons for the cost increase is the need for advanced packaging when employi... » read more

EDA Revenue Up 11% YoY In Q4 ’24


The EDA industry reported substantial revenue growth in Q4 2024, up 11% to $4.9 billion from $4.44 billion reported in the same quarter of 2023, according to the ESD Alliance, a SEMI Technology Community, announced Monday in its latest Electronic Design Market Data (EDMD) report. The four-quarter moving average, which compares the most recent four quarters to the prior four, rose 12.8%. Wald... » read more

Advanced Packaging Fundamentals for Semiconductor Engineers


Advanced packaging is inevitable. Large systems companies and processing vendors already are working with various types of highly engineered packaging. The rest of the semiconductor industry will follow at some point, whether they're designing their own packages, developing the tools, processes, materials, and methodologies to create them, or developing components that will be used inside of th... » read more

Lego-Style Software For Automotive And Industrial Chiplet Systems?


Chiplets are a key topic in the semiconductor industry today, as they offer the potential to greatly increase the performance and flexibility of chips. The current focus is primarily on implementation, in particular on the architecture and the development of die-to-die interfaces that enable efficient communication between the individual chips. These technologies hold out the promise of meeting... » read more

3D-IC Ecosystem Starts To Take Form


The adoption of chiplets is inevitable, but exactly when a mass migration toward this design approach will begin is yet to be determined. Nevertheless, some of the biggest technological and business-related barriers are being addressed. And while a chiplet-based design remains beyond the economic reach of many companies today, that is starting to change. Early signs of an emerging ecosystem ... » read more

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