tag: DFT

Optimizing DFT With AI And BiST
By Gregory Haley - 12 Feb, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to explore how AI impacts design for testability, with Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne; Sri Ganta, director of test products at Synopsys; Dave Armstrong, principal test strategist at Advantest; and Lee Harrison, director of Tessent automotive IC solutions at Siemens EDA. Wh... » read more

Hyperconvergence Of Design For Test And Physical Design
By Sri Ganta - 11 Feb, 2025 - Comments: 0

By Sri Ganta and Hyoung-Kook Kim In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, design cores also comprise DFT (Design for Test) logic that spreads across the design. The DFT logic also must be optimized for PPA, requiring design implemen... » read more

Electronic and Transport Properties of Six TMD Heterostructures
By Technical Paper Link - 24 Jan, 2025 - Comments: 0

A new technical paper titled "Computational Assessment of I–V Curves and Tunability of 2D Semiconductor van der Waals Heterostructures" was published by researchers at Chalmers University of Technology. Abstract "Two-dimensional (2D) transition metal dichalcogenides (TMDs) have received significant interest for use in tunnel field-effect transistors (TFETs) due to their ultrathin layers... » read more

Screening For Known Good Interposers
By Anne Meixner - 14 Jan, 2025 - Comments: 0

Ensuring the quality of silicon and organic interposers is becoming harder as the number of signals passing through them continues to grow, fueled by more chiplets, higher processing demands, and more layers of devices assembled in a package. Interposers initially were viewed as relatively simple conduits. That perception has changed rather dramatically in recent years with the growing focus... » read more

Industry Standards For Chiplets And Their Role In Test
By Jeorge Hurtarte - 14 Jan, 2025 - Comments: 0

As the semiconductor industry increasingly moves to chiplets, 2.5D/3D packaging, and heterogeneous integration, there are significant new challenges for test. Leaders like Teradyne have the technologies necessary to respond and innovate, but to keep the industry running smoothly, we need effective collaboration, and that demands standardization. Source: Arizona State University There ... » read more

No-Compromise Packetized Test Improves DFT Efforts
By Peter Orlando - 14 Jan, 2025 - Comments: 0

Design for Test (DFT) managers often must make difficult and sometimes costly trade-offs between test implementation effort and manufacturing test cost. The traditional method for evaluating these trade-offs has been to use hierarchical DFT methods in a divide-and-conquer approach. In hierarchical DFT efforts, all implementation, including pattern generation and verification, is done at the cor... » read more

DFT At The Leading Edge
By Gregory Haley - 14 Jan, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the rapidly changing landscape of design for testability (DFT), focusing on the impact of advancements in fault models, high-speed interfaces, and lifecycle data analytics, with Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne; Sri Ganta, director of test products at Synopsys; D... » read more

SLM Evolves Into Critical Aspect Of Chip Design And Operation
By Ann Mutschler - 19 Dec, 2024 - Comments: 0

Silicon lifecycle management has evolved greatly in the past five years, moving from novel concept to a key part of design flows at industry leaders such as NVIDIA, Amazon Web Services, Ericsson, and others. Along with becoming a major focus for companies developing semiconductors, the use cases have expanded. While initially focused on post-silicon insights, SLM has expanded to cover the en... » read more

Navigating Increased Complexity In Advanced Packaging
By Gregory Haley - 17 Dec, 2024 - Comments: 1

As chips evolve toward stacked, heterogeneous assemblies and adopt more complex materials, engineers are grappling with new and often less predictable sources of variation. This is redefining what it means to achieve precision, forcing companies to rethink everything from process control and in-line metrology to materials selection and multi-level testing. These assemblies are the result of ... » read more

Testing For Thermal Issues Becomes More Difficult
By Gregory Haley - 10 Dec, 2024 - Comments: 0

Increasingly complex and heterogeneous architectures, coupled with the adoption of high-performance materials, are making it much more difficult to identify and test for thermal issues in advanced packages. For a single SoC, compressing higher functionality into a smaller area concentrates the processing and makes thermal effects more predictable. But that processing can happen anywhere in a... » read more

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