A Lightweight Scan Instrumentation For Enhancing The Post-Silicon Test Efficiency in ICs (U. of Florida)


A technical paper titled "Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation" was published by researchers at University of Florida. Abstract "Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-b... » read more

Better ATPG To Minimize Chip Test Time And Cost


As chips get ever bigger and more complex, the electronic design automation (EDA) industry must innovate constantly to keep up. Engineers expect every new generation of silicon to be modeled, simulated, laid out, and checked in about the same time with the same effort, despite the growth in die size and density. One area of particular focus is manufacturing test. Any effort expended to reduce t... » read more

Shifting Left With DFT To Optimize Productivity, Testability, And Time-To-Market


This paper discusses one of the Siemens EDA shift-left strategies in the RTL-to-signoff flow: shift-left design-for-test (DFT). Tessent RTL Pro software automates the analysis and insertion of Tessent VersaPoint test point technology, LBIST-OST test points, dedicated scan wrapper cells and x-bounding logic as behavioral code at the RTL level. Tessent RTL Pro builds on Tessent’s market-leading... » read more

Identifying Sources Of Silent Data Corruption


Silent data errors are raising concerns in large data centers, where they can propagate through systems and wreak havoc on long-duration programs like AI training runs. SDEs, also called silent data corruption, are technically rare. But with many thousands of servers, which contain millions of processors running at high utilization rates, these damaging events become common in large fleets. ... » read more

Shift Left In DFT Design


The semiconductor industry continues to face numerous challenges as designs approach reticle limits, process nodes evolve and engineering resources become increasingly stretched. It is essential to maintain high productivity and quality throughout the design flow. This keeps projects on schedule, within budget, and ensures they remain high-quality, reliable, yield well and perform as intended. ... » read more

Failure To Launch


Failure analysis (FA) is an essential step for achieving sufficient yield in semiconductor manufacturing, but it’s struggling to keep pace with smaller dimensions, advanced packaging, and new power delivery architectures. All of these developments make defects harder to find and more expensive to fix, which impacts the reliability of chips and systems. Traditional failure analysis techniqu... » read more

Optimizing DFT With AI And BiST


Experts at the Table: Semiconductor Engineering sat down to explore how AI impacts design for testability, with Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne; Sri Ganta, director of test products at Synopsys; Dave Armstrong, principal test strategist at Advantest; and Lee Harrison, director of Tessent automotive IC solutions at Siemens EDA. Wh... » read more

Hyperconvergence Of Design For Test And Physical Design


By Sri Ganta and Hyoung-Kook Kim In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, design cores also comprise DFT (Design for Test) logic that spreads across the design. The DFT logic also must be optimized for PPA, requiring design implemen... » read more

Electronic and Transport Properties of Six TMD Heterostructures


A new technical paper titled "Computational Assessment of I–V Curves and Tunability of 2D Semiconductor van der Waals Heterostructures" was published by researchers at Chalmers University of Technology. Abstract "Two-dimensional (2D) transition metal dichalcogenides (TMDs) have received significant interest for use in tunnel field-effect transistors (TFETs) due to their ultrathin layers... » read more

Screening For Known Good Interposers


Ensuring the quality of silicon and organic interposers is becoming harder as the number of signals passing through them continues to grow, fueled by more chiplets, higher processing demands, and more layers of devices assembled in a package. Interposers initially were viewed as relatively simple conduits. That perception has changed rather dramatically in recent years with the growing focus... » read more

← Older posts