Finding the Scope of CXL-Enabled Tiered Memory System in Production


This new technical paper titled "TPP: Transparent Page Placement for CXL-Enabled Tiered Memory" is presented by researchers at University of Michigan and Meta Inc. Abstract (partial) "We propose a novel OS-level application-transparent page placement mechanism (TPP) for efficient memory management. TPP employs a lightweight mechanism to identify and place hot and cold pages to appropriate... » read more

An Escalation of Rowhammer To Rows Beyond Immediate Neighbors


Researchers at Graz University of Technology, Lamarr Security Research, Google, AWS, and Rivos presented this new technical paper titled "Half-Double: Hammering From the Next Row Over" at the USENIX Security Symposium in Boston in August 2022. Abstract: "Rowhammer is a vulnerability in modern DRAM where repeated accesses to one row (the aggressor) give off electrical disturbance whose cumu... » read more

Data Integrity For JEDEC DRAM Memories


With the DRAM fabrication advancing from 1x to 1y to 1z and further to 1a, 1b, and 1c nodes along with the DRAM device speeds going up to 8533 for LPDDR5 and 8800 for DDR5, data integrity is becoming a really important issue that the OEMs and other users have to consider as part of the system that relies on the correctness of data being stored in the DRAMs for system to work as designed. I... » read more

Reduce RowHammer Vulnerability By Reducing Wordline Voltage


Researchers from ETH Zurich present a new technical paper titled "Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices." Abstract (Partial) "This is the first work to experimentally demonstrate on 272 real DRAM chips that lowering VPP reduces a DRAM chip's RowHammer vulnerability. We show that lowering VPP 1) increases the number of activat... » read more

DRAM Chips That Employ On-Die Error Correction & Related Reliability Techniques


This new PhD thesis paper titled "Enabling Effective Error Mitigation in Memory Chips That Use On-Die Error-Correcting Codes" from ETH Zurich researcher Minesh Patel won the IEEE  William C. Carter Award in June 2022. Abstract "Improvements in main memory storage density are primarily driven by process technology scaling, which negatively impacts reliability by exacerbating various circu... » read more

DDR5: How Faster Memory Speeds Shape The Future


Faster data processing requires faster memory. Double data rate synchronous dynamic random-access memory (DDR SDRAM) enables the world’s computers to work with the data in memory. DDR is used everywhere — not just in servers, workstations, and desktops, but it is also embedded in consumer electronics, automobiles, and other system designs. DDR SRAM is used for running applications and d... » read more

End to End System Design for DRAM-based TRNG


Research paper titled "DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators" is presented from researchers at TOBB University of Economics and Technology and ETH Zurich. Abstract "Random number generation is an important task in a wide variety of critical applications including cryptographic algorithms, scientific simulations, and industrial testing tools. True ... » read more

ETH Zurich: PIM (Processing In Memory) Architecture, UPMEM & PrIM Benchmarks


New paper technical titled "Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture" led by researchers at ETH Zurich. Researchers provide a comprehensive analysis of the first publicly-available real-world PIM architecture, UPMEM, and introduce PrIM (Processing-In-Memory benchmarks), a benchmark suite of 16 workloads from different application domai... » read more

Chipmaking In The Third Dimension


Every few months, new and improved electronics are introduced. They’re typically smaller, smarter, faster, have more bandwidth, are more power-efficient, etc. — all thanks to a new generation of advanced chips and processors. Our digital society has come to expect this steady drip of new devices as sure as the sun will rise tomorrow. Behind the scenes, however, engineers are working feve... » read more

DRAM Thermal Issues Reach Crisis Point


Within the DRAM world, thermal issues are at a crisis point. At 14nm and below, and in the most advanced packaging schemes, an entirely new metric may be needed to address the multiplier effect of how thermal density increasingly turns minor issues into major problems. A few overheated transistors may not greatly affect reliability, but the heat generated from a few billion transistors does.... » read more

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