tag: design for test

An Optimal Path To DFT Automation
By Jay Jahangiri - 11 Feb, 2020 - Comments: 0

To keep up with time-to-market demands when SoCs keep increasing in size and complexity requires the adoption of better DFT flows and technologies. One of the most successful changes in design-for-test (DFT) flows in recent years has been the deployment of hierarchical DFT. Taking the divide-and-conquer approach delivers real savings in test time and cost, plus keeps DFT out of the critical pat... » read more

Verification Pilgrims Show A Historical Case For DFT
By Lee Vick - 27 Nov, 2019 - Comments: 0

The Mayflower Steps, where the Pilgrims are believed to have embarked on their journey to America, are located in the beautiful Barbican area of Plymouth, a small town in the southwest of England. As the lone American working for Moortec, a British company based in Plymouth, I stood and stared at them this past September. Separated by a few yards of distance but 399 years of history I found my... » read more

The Great Test Blur
By Ed Sperling - 06 Aug, 2019 - Comments: 0

As chip design and manufacturing shift left and right, concerns over reliability are suddenly front and center. But figuring out what exactly what causes a chip to malfunction, or at least not meet specs for performance and power, is getting much more difficult. There are several converging trends here, each of which plays an integral role in improving reliability. But how significant a role... » read more

BiST Grows Up In Automotive
By Ann Mutschler - 12 Jun, 2019 - Comments: 0

Test concepts and methods that have been used for many years in traditional semiconductor and SoC design are now being leveraged for automotive chips, but they need to be adapted and upgraded to enable monitoring of advanced automotive systems during operation of a vehicle. Automotive and safety critical designs have very high quality, reliability, and safety requirements, which pairs pe... » read more

Smart Plug-And-Play DFT For Arm Cores
By Ron Press - 11 Jun, 2019 - Comments: 0

Modern SoCs are experiencing continued growth in capabilities and design sizes with more and more subsystem IPs being implemented. These large, complex, multi-core SoCs need strategies for DFT and ATPG that effectively reduce DFT effort, minimize ATPG runtime, and still achieve the target test coverage. Hierarchical DFT enables designing and testing of these designs in a systematic and repeatab... » read more

Automotive, AI Drive Big Changes In Test
By Ann Mutschler - 25 Apr, 2019 - Comments: 0

Design for test is becoming enormously more challenging at advanced nodes and in increasingly heterogeneous designs, where there may be dozens of different processing elements and memories. Historically, test was considered a necessary but rather mundane task. Much has changed over the past year or so. As systemic complexity rises, and as the role of ICs in safety-critical markets continues ... » read more

How To Manage DFT For AI Chips
By Rahul Singhal - 09 Apr, 2019 - Comments: 0

Semiconductor companies are racing to develop AI-specific chips to meet the rapidly growing compute requirements for artificial intelligence (AI) systems. AI chips from companies like Graphcore and Mythic are ASICs based on the novel, massively parallel architectures that maximize data processing capabilities for AI workloads. Others, like Intel, Nvidia, and AMD, are optimizing existing archite... » read more

Building Bridges: A New DFT Paradigm
By Robert Ruiz - 28 Mar, 2019 - Comments: 0

Over the last twenty years, structural testing with scan chains has become pervasive in chip design methodology. Indeed, it’s remarkable to think that most electronic devices we interact with today (think smartphones, laptops, televisions, etc.) contain hundreds to thousands of interconnected scan chains used to verify that the semiconductors were manufactured without defects. Because the imp... » read more

Why Analog Designs Fail
By Brian Bailey - 14 Feb, 2019 - Comments: 2

The gap between analog and digital reliability is growing, and digital designs appear to be winning. Reports show that analog content causes the most test failures and contributes significantly more than digital to field returns. The causes aren't always obvious, though. Some of it is due to the maturity of analog design and verification. While great strides have been made in digital circuit... » read more

Concurrent Test
By Ed Sperling - 11 Jan, 2019 - Comments: 0

Derek Wu, senior staff applications engineer at Advantest, looks at the need for doing multiple tests at the same time as chip designs become more complex, increasingly heterogeneous, and much more difficult to test at advanced nodes. https://youtu.be/-8inbjX_af0       __________________________________ See more tech talk videos here. » read more

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