Monday At DAC

By Brian Bailey - 20 Jun, 2017 - Comments: 1

The 54th DAC got started today in a very steamy Austin. While we may be a maturing industry, there is certainly no indications that the people within the industry have given up or intend to take it easy. The event really got started late Sunday when Laurie Balch, chief analyst for Gary Smith EDA, delivered her message. She said that the focus is becoming the verticals. "This change in focus is ... » read more

Safety Plus Security: A New Challenge

By Brian Bailey - 08 Jun, 2017 - Comments: 0

Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry's attention. And after that, it's not always clear how to best implement solutions or what the tradeoffs are between cost, performance, and risk versus benefit. Putting safety and security in the same basket is a ... » read more

Chip Test Shifts Left

By Jeff Dorsch - 07 Jun, 2017 - Comments: 0

“Shift left” is a term traditionally applied to software testing, meaning to take action earlier in the V-shaped time line of a project. It has recently been touted in electronic design automation and IC design, verification, and test. “Test early and test often” is the classic maxim of software testing. What if that concept could also be implemented in semiconductor testing, to redu... » read more

What’s Next In Scaling, Stacking

By Mark LaPedus - 05 Jun, 2017 - Comments: 9

An Steegen, executive vice president of semiconductor technology and systems at [getentity id="22217" e_name="Imec"], sat down with Semiconductor Engineering to discuss IC scaling, chip stacking, packaging and other topics. Imec is an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Chipmakers are shipping 16nm/14nm processes with 10nm and 7nm technologies... » read more

Foundry Wars, Take Two

By Ed Sperling - 25 May, 2017 - Comments: 0

Samsung, GlobalFoundries, TSMC and Intel all have declared their intention to fill in nearly every node possible with multiple processes, different packaging options, and new materials. In fact, the only number that hasn't been taken so far is 9nm. It's not that one foundry's 10nm is the same as another's. Each company defines its nodes differently, and these days comparing nodes is almost m... » read more

Reworking Established Nodes

By Ed Sperling - 24 May, 2017 - Comments: 2

New technology markets and a flattening in smartphone growth has sparked a resurgence in older technology processes. For many of these up-and-coming applications, there is no compelling reason to migrate to the latest process node, and equipment companies and fabs are rushing to fill the void. As with all electronic devices, the focus is on cost-cutting. But because these markets are likely ... » read more

Calibre Evolves Constantly

By Mike Santarini - 11 May, 2017 - Comments: 0

I find it truly amazing that despite the constantly changing tide in the digital IC design industry that some tools have remained in that number 1 spot for over a decade. The three tools that immediately come to mind are Synopsys’ PrimeTime and Design Compiler and Mentor’s Calibre. I remember back when I first started covering the industry in the mid-1990s that Quad Design’s Motive sta... » read more

The Rise Of Parallelism

By Ed Sperling - 27 Apr, 2017 - Comments: 1

Parallel computing is an idea whose time has finally come, but not for the obvious reasons. Parallelism is a computer science concept that is older Moore's Law. In fact, it first appeared in print in a 1958 IBM research memo, in which John Cocke, a mathematician, and Daniel Slotnick, a computer scientist, discussed parallelism in numerical calculations. That was followed eight years later by... » read more

Researchers Learn New Tricks

By Brian Bailey - 27 Apr, 2017 - Comments: 0

There is very little EDA research being done in universities today, except for very narrow fields such as [getkc id="33" kc_name="formal verification"]. It has been a steady decline over quite a long period of time. There are several reasons for this. The first is money. Money has to flow into the universities to pay for the research, and this has to lead to some form of prestige for the est... » read more

Avoiding A $7.7B Chip Design Cost

By Frank Schirrmeister - 27 Apr, 2017 - Comments: 0

For years, the story about semiconductor development cost and about EDA contributions has been pretty simple. Cost has been, is, and will likely be for a while, the single biggest issue in scaling development for more complex designs. The next big leap for verification productivity will be the close integration of verification and design engines, both vertically and horizontally as I have writt... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.