tag: fan-out

Angstrom-Level Measurements With AFMs
By Mark LaPedus - 19 Aug, 2021 - Comments: 0

Competition is heating up in the atomic force microscopy (AFM) market, where several vendors are shipping new AFM systems that address various metrology challenges in packaging, semiconductors and other fields. AFM, a small but growing field that has been under the radar, involves a standalone system that provides surface measurements on structures down to the angstrom level. (1 angstrom = 0... » read more

Ultra-Small Fan-Out Packaging Solution
By Ken Hsiao - 19 Aug, 2021 - Comments: 0

With the advent of the Internet and multimedia, electronics miniaturization in the form of integrated circuits has become an indispensable part of our lives. To ensure its long-term operation and reliability, the rapid development of integrated circuits depends on advancements in not only the design and manufacturing of chips, but also its packaging. As the market demand for consumer and com... » read more

Piecing Together Chiplets
By Mark LaPedus - 22 Jul, 2021 - Comments: 3

Several companies are implementing the chiplet model as a means to develop next-generation 3D-like chip designs, but this methodology still has a long way to go before it becomes mainstream for the rest of the industry. It takes several pieces to bring up a 3D chip design using the chiplet model. A few large players have the pieces, though most are proprietary. Others are missing some key co... » read more

What Does It Take To Build A Successful Multi-Chip Module Factory?
By Mike McIntyre - 06 Jul, 2021 - Comments: 0

When it comes to multi-chip module (MCM) manufacturing, fan-out wafer-level and fan-out panel-level packaging have received a lot of coverage recently. Every week, it seems like there is an announcement about “Company XYZ” moving their products into the fan-out wafer-level packaging (FOWLP) or fan-out panel-level packaging (FOPLP) space. But these moves come with challenges that didn’t ex... » read more

Fan-Out Packaging Options Grow
By Mark LaPedus - 17 Jun, 2021 - Comments: 0

Chipmakers, OSATs and R&D organizations are developing the next wave of fan-out packages for a range of applications, but sorting out the new options and finding the right solution is proving to be a challenge. Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and sma... » read more

Advanced Packaging’s Next Wave
By Mark LaPedus - 20 May, 2021 - Comments: 0

Packaging houses are readying the next wave of advanced packages, enabling new system-level chip designs for a range of applications. These advanced packages involve a range of technologies, such as 2.5D/3D, chiplets, fan-out and system-in-package (SiP). Each of these, in turn, offers an array of options for assembling and integrating complex dies in an advanced package, providing chip custo... » read more

Making Chip Packaging More Reliable
By Mark LaPedus - 15 Apr, 2021 - Comments: 0

Packaging houses are readying the next wave of IC packages, but these products must prove to be reliable before they are incorporated into systems. These packages involve several advanced technologies, such as 2.5D/3D, chiplets and fan-out, but vendors also are working on new versions of more mature package types, like wirebond and leadframe technologies. As with previous products, packaging... » read more

What Goes Wrong In Advanced Packages
By Ed Sperling - 24 Mar, 2021 - Comments: 1

Advanced packaging may be the best way forward for massive improvements in performance, lower power, and different form factors, but it adds a whole new set of issues that were much better understood when Moore's Law and the ITRS roadmap created a semi-standardized path forward for the chip industry. Different advanced packaging options — system-in-package, fan-outs, 2.5D, 3D-IC — have a... » read more

Surviving The Three Phases Of High Density Advanced Packaging Design
By Siemens EDA - 24 Feb, 2021 - Comments: 0

The growth of High Density Advanced Packages (HDAP) such as FOWLP, CoWoS, and WoW is triggering a convergence of the traditional IC design and IC package-design worlds. To handle these various substrate scenarios, process transformation must occur. This paper discusses the three phases of HDAP design and provides tips on how to survive their challenges. To read more, click here. » read more

WLFO For High-Performance Low-Cost Packaging Of RFMEMS-CMOS
By Amkor - 17 Feb, 2021 - Comments: 0

Navigating the trade-offs between performance, size, cost and reliability can be a challenge when considering integrated circuit (IC) packaging and the end-application. The integration of micro-electromechanical systems (MEMS), either monolithic or heterogeneous, introduces yet another level of complexity that has only recently been a major focus of multi-device packaging. Wafer-level fanout (W... » read more

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