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Making Chip Packaging More Reliable

Challenges rise for both advanced packages and for new innovations in older technologies.


Packaging houses are readying the next wave of IC packages, but these products must prove to be reliable before they are incorporated into systems.

These packages involve several advanced technologies, such as 2.5D/3D, chiplets and fan-out, but vendors also are working on new versions of more mature package types, like wirebond and leadframe technologies. As with previous products, packaging houses are quick to point out that their new packages are reliable, but unforeseen problems can sometimes occur in the field.

Packaging is a confusing landscape with a plethora of buzzwords and too many options. The one constant is that each package must meet a given reliability spec, meaning it must perform its intended function without failure over a period of time. Still, even if a product meets spec, there are several unknowns and variables regarding reliability. Next-generation chips housed in the latest packages are subjected to a bevy of harsh operating conditions in systems, especially in automotive, military/aerospace, and inside of data centers.

Concerns about reliability aren’t new in the semiconductor industry, and they have been growing recently as advanced semiconductor and packaging content continues to rise in mission-critical systems. Most, if not all, products can wear out over time due to a variety of factors. The key is being able to predict and prevent failures, and determining the acceptable range of operating conditions for a particular part.

This isn’t as simple as it seems. “Reliability has always been important,” said Eric Beyne, senior fellow, vice president of R&D and director of the 3D system integration program at Imec. “The package is where the chip meets the environment, which is not always friendly to devices. You have humidity and ionic contamination, as well as tropical or freezing conditions. All these things can occur at one time or another.”

Packages are also subjected to harsh operating conditions in systems, as well as various interactions with the chips themselves. “They call it chip-package interaction (CPI). It’s an interaction between the reliability of the chips and the package. There might be high mechanical stresses and torsion,” Beyne said. “Previously, you thought about a completely separate world of chip and package testing. In this case, you cannot completely separate the two because they interact.”

That’s just the tip of the iceberg for packaging reliability. To help the industry gain some insights, Semiconductor Engineering has taken a look at a few package types and some of the reliability issues at hand. Wirebond, quad-flat no-lead (QFN), fan-out and 3D architectures are explored.

Reliability issues/testing
Reliability often is confused with quality, which is when a product satisfies its stated needs. The goal for any product is to achieve zero failures in the field. In operation, a product may work for a set period — or forever. But at times, it may wear out or fail.

That’s where reliability fits in. To ensure product reliability, IC vendors for years have followed the same steps:

  • It’s not good enough to test a device based on the spec sheet, so vendors run various accelerated/stress tests on a device. The goal is to cause a device to fail.
  • Then, a vendor searches for the failure mechanisms and solves any potential problems.
  • From there, models are developed and used to predict a product lifetime under normal conditions.

In this process, devices are subjected to a battery of tests. For example, high temperature reverse bias (HTRB), one common test, examines the degradation of a device under temperature. For this, devices are placed in a specialized HTRB burn-in test system and subjected to high voltages and temperatures.

Once the devices meet spec, they are shipped to a packaging house, where they are packaged and tested. Along the way, packaged parts also undergo a separate round of reliability tests.

Vendors want to look at the package under harsh conditions. That way, they can make any changes to the product if needed. It also helps predict the product lifetime under normal application stress.

Among the accelerated tests used in packaging include thermal cycling, shock tests, high temperature and humidity (HAST) test, mechanical stress, and drop test.

Not all packages have the same reliability test requirements. Automotive and military/aerospace have more rigid specs than consumer. Depending upon a variety of factors, though, a given product may pass every test in the lab but still encounter issues in the field.

“Originally, the idea was that these types of tests would predict the lifetime of a product. When you do an accelerated test, you try to obtain a prediction for a test at room temperature over a longer time,” Imec’s Beyne said. “The reality is that, of course, these tests are often far away from real life conditions. You can’t just assume that the same mechanism happens at room temperature. You also risk that some of these tests will cause over engineering. And there may be things that you overlooked.”

All told, reliability testing is important. But it’s equally important to ensure the product is reliable from the very beginning. “You can have mechanical, thermal and chemical stress. There’s risk in everything. But it’s really about how you mitigate that risk upfront in the design stage,” said Sam Sadri, senior process engineer at QP Technologies.

Wirebond reliability
Some 75% to 80% of today’s packages are based on wire bonding, according to TechSearch. A wire bonder stitches one chip to another chip or substrate using tiny wires. Wire bonding is used for low-cost legacy packages, midrange packages, and memory die stacking.

Figure 1: Wirebond wires in packages Source: K&S

Figure 1: Wirebond wires in packages Source: K&S

Over the years, wire bonders have become more advanced as well as customized for specific applications. For example, Kulicke & Soffa (K&S) has introduced bonders targeted for the cost-performance, high-end, LED and memory markets.

“We are adding smart sensing and adaptive control to our next-generation machines,” said Bob Chylak, CTO of K&S. “This capability will look for yield excursions due to application, tool, material, or bonder variation. It will also provide for predictive maintenance. The goal is for more and more factory machines to run identically and flawlessly with less operators needed.”

Advanced bonders enable packages with more die stacks at finer pitches. “The state-of-the-art for pitch is about 40μm. The bonders are capable of going to finer pitch, but there is no industry need today. In terms of stacked die, we have 8 and even 16 die stacks in production. We have done some wild prototypes with up to 128 die. The bonding does not seem to be the limit,” Chylak said. “It is very common to have four or more rows of pads on the device. This multi-tier pad layout enables more than 1,000 I/Os for wire-bonded devices, making wire bond more of an area technology instead of a peripheral technology. Wire bonding looping design and programming can be very challenging for these kind of devices.”

To prevent any mishaps, wire bonders from K&S and others have real-time electric test functions, which check the electric connectivity after each bond. This ensures high yields during the process.

Reliability issues can occur, though. In the 2010s, many IC vendors migrated from gold to copper wiring for wire bonded packages. Gold, the dominate wire type at that time, was too expensive for many applications. Today, copper-based wirebonded packages dominate the landscape, but gold is still used.

Copper is inexpensive with high conductivity, but it sometimes is prone to corrosion, causing failure in wirebonded packages. This is due to halogens ions in chloride, which are present in mold compounds and other sources.

HAST is used to test for corrosion. In a system, a package is subjected to 85% humidity at 130°C.

To prevent failures, tool and material vendors must collaborate early in the process. “The idea is to make the compound halogen-free, but not so halogen-free that it has an exorbitant cost,” Chylak said.

There are other issues that can crop up, too. “During the bonding itself, the main issues are caused by material variation, contamination or premature tool wear. This is actually rare,” he said. “For a packaged wire bonded IC, there are two things to consider — the qualification of the process for high-volume assembly and the life of the part after assembly.”

For this, there are various reliability tests, such as temperature cycling, biased HAST, and high-temperature storage life test (HTSL). Biased HAST puts a voltage on the device and subjects it to high pressure and temperature, according to EAG Laboratories. HTSL measures device resistance to a high-temperature environment, according to EAG.

Wirebonders are used to make several package types, such as QFN and quad flat-pack (QFP). These belong in the leadframe group of package types. A leadframe is a metal frame. In the production process, a die is attached to the frame and connected.

QFN and QFP are used in automotive, consumer, mil-aero, RF and other markets. “One advantage with QFN is the exposed die paddle,” QP’s Sadri said. “That exposed die paddle on the bottom gives you better thermals. If you compare the thermal impedance of the same package with leads versus a QFN with no leads, the thermal impedance is half of the leaded counterpart.”

QFN is a mature technology, although they are becoming more complex. “QFNs go as little as a couple of millimeters square with 4 and 6 leads, up to 12mm x 12mm square. Then, in between 3 and 12 millimeters, there are all these other flavors with different sizes,” Sadri said. “We have seen a QFN that are 6mm x 6mm, and have dropped 15 components in there. We’ve seen some stacking there, too. It’s basically a system-in-a-package inside a small QFN. What’s in the future with QFN? A lot more I/Os. I see more things happening with customized QFN in RF applications.”

There are some issues, however. Typically, QFN can withstand 1,000 thermal cycles. In comparison, a leaded QFP can withstand up to 10,000 thermal cycles, -40°C to 125°C.

QFP is a leaded package with no solder joints. QFN makes use of solder joints. Under certain loads over time, solder joints can undergo fatigue. “Customers will include thermal cycle testing as part of their qualification process for QFN packages. Temperature cycling can be used to measure the solder joint long-term reliability,” said Rosie Medina, vice president of sales and marketing at QP Technologies.

Moisture sensitivity level (MSL) test is also common. “MSL testing is performed to identify the classification level of non-hermetic SMD (surface-mounted devices) that are sensitive to moisture-induced stress,” QP’s Sadri said.

Advanced packages: fan-out, 3D
Meanwhile, advanced packaging is gaining steam. Fan-out, one advanced package type, is used in consumer, industrial and mobile applications. In one example of fan-out, a DRAM die is stacked on top of a logic chip in the package.

Fig. 2: Different options for high-performance compute packaging, interposer-based 2.5D vs. Fan-Out Chip on Substrate (FOCoS). Source: ASE

Fig. 2: Different options for high-performance compute packaging, interposer-based 2.5D vs. Fan-Out Chip on Substrate (FOCoS). Source: ASE

In the fan-out flow, the chips on the wafer are diced and placed in a wafer-like structure, which is filled with an epoxy mold compound. This is called a reconstituted wafer.

Then, redistribution layers (RDLs) are formed in the package. RDLs are the copper metal connection traces that electrically connect one part of the package to another. RDLs are measured by line and space, which refer to the width and pitch of a metal trace.

Fig. 3: Cross section of the bottom of an RDL substrate. Source: Amkor

Fig. 3: Cross section of the bottom of an RDL substrate. Source: Amkor

During the flow, however, the wafer-like structure is prone to warpage. Then, when the dies are embedded in the compound, they tend to move, causing a effect called die shift. This impacts the yield.

Still, fan-out is making inroads and moving in different directions. In 5G, for example, several vendors have developed fan-out antenna-in-package technology. This package combines an RF chip and the antenna in the same unit, which boosts the signal in systems.

“We’re seeing a lot of interest in 5G, whether it’s 39GHz or 60GHz, or 28GHz today, and the reason is the antennas,” said Yin Chang, senior vice president at ASE. “Even before 5G, we were looking at almost 12 antennas in a cell phone. We need one for WiFi, one for Bluetooth, one for GPS, and maybe four to six for LTE frequencies. On top of that, we have to fit three to four additional 5G antennas. There are opportunities for us to integrate those antennas into the package itself because the phone cannot get any bigger. Everybody wants thinner phones and a lot more functions. So for us to do all this in a fan-out package, you need to reduce the overall form factor, whether you use a hybrid substrate or a fan-out with RDL on top of the chip to create this antenna solution.”

In another application, fan-out is incorporating more I/Os with finer RDLs, enabling advanced multi-die products. In a recent paper, TSMC described an ultra-high density fan-out package with RDLs at 0.8µm line/space. Typically, fan-out incorporates RDLs at 2µm line/space and above. A fan-out package with 0.8µm line/space enables 4X more bandwidth than 2µm line/space, according to TSMC.

In RF, ultra-density and other apps, fine-pitch RDLs have some challenges. “In this case, deploying finer line RDL would induce higher resistance theoretically,” said T. Ko, a researcher at TSMC in a recent paper at ECTC. “This resistance rising would impact the data rate correspondingly, which would be detrimental to total bandwidth.”

In its work, TSMC looked at two failure mechanisms for the RDLs — electromigration and stress-migration. Electromigration, which can cause voids and failures in a device, refers to the displacement of the atoms as a result of current flowing through a conductor. Stress migration can form voids, leading to resistance in chips.

To understand these failure mechanisms, TSMC conducted several reliability tests, such a thermal cycling, HAST and HTSL. That’s just for the RDLs. Other parts of the package may require similar or different tests.

Today, meanwhile, the industry is developing a new class of 2.5D/3D packages. In one example, using a chiplet methodology, Intel recently introduced a 3D CPU platform.

Chiplets are the latest craze in packaging. For this, a chipmaker may have a menu of modular dies, or chiplets, in a library. Customers can mix-and-match the chiplets and connect them using a die-to-die interconnect scheme in a package.

The idea behind chiplets is to break up a larger monolithic die into smaller dies. “There are so many different ways to take a big die and break it up into something that works better, and hopefully for lower cost,” said Mike Kelly, vice president of advanced packaging development and integration at Amkor. “It’s certainly easier to get to time to market faster, because you don’t have to do a custom design on every last die. You can do some reuse. But there are different ways customers are approaching that. You have companies doing small CPU chiplets and a big I/O die. There are other people who have decided not to break it up like that. They have discrete units that are all the same, which can be scaled up and down for performance or price point.”

In these architectures, dies also can be stacked on top of each other. For this, tiny copper microbumps and pillars are formed on the top of each die. One die is flipped and the bumps on each side of the dies are bonded together. Bumps and pillars provide small, fast electrical connections between different devices.

The most advanced microbumps/pillars are tiny structures with a 40μm pitch. Using existing equipment, the industry can scale the bump pitch to at least 20μm, and perhaps beyond.

“As the bumps become smaller, electromigration needs to be considered, because the current density will increase,” Imec’s Beyne said. “And, of course, you have thermal hotspots. These things can get very hot. They may also cause local pressures because of thermal gradients.”

At some point, microbump technology will run out of steam. Then, the industry needs a new interconnect technique, namely copper hybrid bonding.

In copper hybrid bonding, a wafer is processed in the fab. Metal pads are formed on the surface of a wafer. A separate wafer undergoes a similar process. The two wafers are bonded.

In a recent paper, Imec assessed the thermal, mechanical and reliability performance of wafer-to-wafer hybrid bonded wafers at 2.5μm pitches. Imec devised and stacked 65nm chips.

“Hybrid pad pitches continue scaling down to sub-μm dimensions, increasing the interconnect densities and decreasing the pad contact area,” said Vladimir Cherman, a researcher from Imec, in the paper. “These two factors may jeopardize electrical performance of hybrid interconnects and their thermo-mechanical stability during packaging and/or reliability tests.”

That’s not the only issue. “One of the things with these architectures, particularly these complex systems, is that you end up with large silicon structures or other structures that you need to stack onto a package,” Imec’s Beyne said. “You still need a laminate package. So there are reliability concerns of the package with a very big die. If you put all of this onto another substrate, there is a mismatch that you have to control between the two. As the system becomes bigger, this problem becomes bigger. You have things like warpage, but that’s more of a fabrication problem than a reliability problem. That can cause a failure at times.”

In Imec’s work, researchers developed a 4-point mechanical bending test. This is used to mimic the thermo-cycling effects in IC packages.

“If do you bonding, you study the fundamental physical behavior of whether it fails or not,” Beyne said. “What it comes down to after that is having the metrology to detect when anything goes wrong. If something goes wrong in the processing, there are issues like voids or particles. These are potentially big issues for reliability. You need to do some good analysis and methodology in inspection.”

Process control is critical for other reasons. A bad die in a chiplet design can cause the entire package to fail. The problems may occur at the die or the material level. “The process control challenges are definitely greater in the smaller nodes,” said Julie Ply, director of quality materials at Brewer Science. “The value of the smaller node materials typically increases, making early detection and correction more important than ever to mitigate potential losses.”

Packaging is becoming more important across the industry. It’s a way to develop complex system-level designs.

So the package must be reliable. But ensuring reliability is not always as easy and must be better understood.

— Ed Sperling contributed to this report.

Related Stories
What Goes Wrong In Advanced Packages
More heterogeneous designs and packaging options add challenges across the supply chain, from design to manufacturing and into the field.

Momentum Builds For Advanced Packaging
Increasing density in more dimensions with faster time to market.

The Race To Much More Advanced Packaging
Hybrid bonding opens up a big improvement in die-to-die performance, but getting there is not trivial.

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