Incremental Design Methodologies

By Brian Bailey - 26 Feb, 2015 - Comments: 0

There are times when we become stuck in the past, or choose to believe something that is no longer true or actually never was true. As we get older, we are all guilty of that. History tends to rewrite itself, especially given that this industry is aging. One of these situations occurred recently, and comments from an industry luminary didn’t align with the thoughts and memories of other peopl... » read more

With Responsibility Comes Power

By Brian Bailey - 12 Feb, 2015 - Comments: 0

The debate continues as to whether [getkc id="106" kc_name="power"] has risen to become a primary design consideration, or if it remains secondary to functionality and performance. What is indisputable is the rise in the importance of both power and energy conservation. As technology improves, additional aspects of the design flow are being affected. With that, the focus for power reduction is ... » read more

An Architectural Choice Overdue For Change

By Brian Bailey - 04 Dec, 2014 - Comments: 0

The past appears to be a lot simpler than the present and when we look into the future, the right decisions often look highly uncertain. This is the value of hindsight, but also includes the notion that the winner gets to write history. What semiconductors look like today could have been very different if different decisions had been made 20 years ago. What if the industry had adopted a paralle... » read more

More Than Moore

By Ed Sperling - 15 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

The Week In Review: Design

By Ed Sperling - 08 Aug, 2014 - Comments: 0

Tools Cadence rolled out a custom power integrity tool for dealing with transistor-level electromigration and IR drop with SPICE-level accuracy. It works in conjunction with the company’s existing power integrity tool for cell-level power signoff. Open-Silicon established a high-speed SerDes technology center of excellence to speed design and production of ASICs using high-speed serial co... » read more

Improving Yield Of 2.5D Designs

By Ann Mutschler - 18 Apr, 2014 - Comments: 0

While progress is being made on the packaging side of 2.5D design, more needs to be resolved when it comes to improving yields. Proponents of 2.5D present compelling benefits. Arif Rahman, a product architect at Altera, noted that the industry trend of silicon convergence is leading to multiple technologies being integrated into single-chip solutions. “2.5D/3D integration has multiple adva... » read more

Performance Still Trumps Power

By Brian Bailey - 16 Jan, 2014 - Comments: 2

When it comes to technology, the past was always simpler than the present and the future looks daunting. In part, this is because finding a solution to a problem allows us to discover the next problem. Over time, the previous problem becomes more understood and solutions improve to the point where it is no longer considered a problem. It was a fairly easy choice about how to implement functiona... » read more

Don’t miss Fully-Depleted Tech Symposium during IEDM (SF)

By Various Writers - 04 Dec, 2012 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~ ~ If you want to cut through the noise surrounding the choices for 28nm and beyond, an excellent place to start is the SOI Consortium’s Fully Depleted Technology Symposium. As a member of the design and manufacturing communities, this is your chance to see and hear what industry leaders are actually doing. Planar? F... » read more

FPGA Design And Verification in Mechatronic Applications

By Various Writers - 23 Aug, 2012 - Comments: 0

The biggest challenge in using FPGA devices may be one of methodology. FPGA designers are familiar with HDL-based requirements-driven design methodologies for digital electronics. But how can requirements be expressed for a system that, while it contains digital elements, is fundamentally non-digital? Fortunately an executable HDL exists that extends the capabilities of the digital VHDL languag... » read more

Integrated IP Goes Vertical

By Ed Sperling - 25 Mar, 2010 - Comments: 0

By Ed Sperling The consolidation of intellectual property from small developers to large players with integrated IP blocks is accelerating. Large IP companies are now developing integrated suites that are pre-tested for specific vertical markets, and new companies are sprouting up to make it easier to put even broader collections of IP together in meaningful ways. It’s difficult to te... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?