tag: FPGA

Heterogeneous Redundant Circuit Design Approaches for FPGAs
By Technical Paper Link - 12 Jul, 2022 - Comments: 0

New research paper titled "Evaluation of Directive-based Heterogeneous Redundant Design Approaches for Functional Safety Systems on FPGAs" from researchers at Nagasaki University. Abstract (Partial) "In this paper, we present and evaluates two heterogeneous redundant circuit design approaches for FPGAs: a resource-level approach and strategy-level approach. The resource-level approach foc... » read more

Delay-based PUF for Chiplets to Verify System Integrity
By Technical Paper Link - 08 Jul, 2022 - Comments: 0

New technical paper titled "Know Time to Die – Integrity Checking for Zero Trust Chiplet-based Systems Using Between-Die Delay PUFs" by researchers at University of Massachusetts, Amherst MA, Abstract (partial): "In this paper we propose a delay-based PUF for chiplets to verify system integrity. Our technique allows a single chiplet to initiate a protocol with its neighbors to measure un... » read more

eFPGAs Bring A 10X Advantage In Power And Cost
By Andy Jaros - 07 Jul, 2022 - Comments: 0

eFPGA LUTs will out-ship FPGA LUTs at some point in the near future because of the advantages of reconfigurable logic being built into the chip: cost reduction, lower power, and improved performance. Many systems use FPGAs because they are more efficient than processors for parallel processing and can be programmed with application specific co-processors or accelerators typically found in da... » read more

TU Dresden: Tile-based Multi-Core Architecture for Heterogeneous RISC-V Processors Suitable for FPGA Platforms
By Technical Paper Link - 04 Jul, 2022 - Comments: 0

New technical paper titled "AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors" from researchers at Technische Universitaet Dresden (TU Dresden). Partial Abstract: "In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heter... » read more

HBM-based scalable multi-FPGA emulator for Quantum Fourier Transform (QFT)
By Technical Paper Link - 01 Jul, 2022 - Comments: 0

New technical paper titled "A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory" from researchers at Tohoku University in Japan. Abstract: "Quantum computing is regarded as the future of computing that hopefully provides exponentially large processing power compared to the conventional digital computing. However, current quantum computers do not... » read more

CORDIC-based Chip Design With Iterative Pipelining Architecture for Biped Robots
By Technical Paper Link - 03 Jun, 2022 - Comments: 0

New technical paper titled "Efficient and Accurate CORDIC Pipelined Architecture Chip Design Based on Binomial Approximation for Biped Robot," from researchers at Chung Yuan Christian University (Taiwan) and Ateneo de Manila University (Philippines). Abstract: "Recently, much research has focused on the design of biped robots with stable and smooth walking ability, identical to human bein... » read more

Software Controlled Modular FPGA
By Flex Logix - 01 Jun, 2022 - Comments: 0

Flex Logix has developed embedded FPGA IP (EFLX® embedded FPGA or eFPGA) that has been licensed for use in many commercial, aerospace and defense programs. It has also developed an edge inferencing accelerator, InferX® to efficiently process AI edge inferencing workloads requiring high throughput for the least power and area. This paper describes managing and dynamically programming eFPGA des... » read more

Kria KR260 Robotics Starter Kit: Unleashing Roboticists Through Hardware Acceleration
By AMD - 01 Jun, 2022 - Comments: 0

The Kria™ KR260 Robotics Starter Kit is a Kria SOM-based development platform for robotics and factory automation applications. It enables roboticists and industrial developers without FPGA expertise to develop hardware accelerated applications for robotics, machine vision, industrial communications and control. Developers benefit with greater flexibility from native ROS 2 (Humble Hawksb... » read more

CFU Playground: Significant Speedups & Design Space Exploration Between CPU & Accelerator
By Technical Paper Link - 30 May, 2022 - Comments: 0

Technical paper titled "CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs," from Google, Purdue University and Harvard University. Abstract "We present CFU Playground, a full-stack open-source framework that enables rapid and iterative design of machine learning (ML) accelerators for embedded ML systems. Our toolchain tightly integr... » read more

Repositioning For A Changing IC Market
By Ed Sperling - 26 May, 2022 - Comments: 0

Sailesh Chittipeddi, executive vice president at Renesas, sat down with Semiconductor Engineering to talk about how changes in end markets are shifting demand for technology. What follows are excerpts of that conversation. SE: Renesas has acquired a number of companies over the past several years. What's the goal? Chittipeddi: The goal very simply is to create an industry leading solutio... » read more

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