tag: functional verification

Can ML Help Verification? Maybe
By Brian Bailey - 22 Sep, 2022 - Comments: 0

Functional verification produces an enormous amount of data that could be used to train a machine learning system, but it's not always clear which data is useful or whether it can help. The challenge with ML is understanding when and where to use it, and how to integrate it with other tools and approaches. With a big enough hammer, it is tempting to call everything a nail, and just throwing ... » read more

Is AI Improving A Broken Process?
By Brian Bailey - 26 May, 2022 - Comments: 0

Verification is fundamentally comparing two models, each derived independently, to find out if there are any different behaviors expressed between the two models. One of those models represents the intended design, and the other is part of the testbench. In an ideal flow, the design model would be derived from the specification, and each stage of the design process would be adding other deta... » read more

Shifting The Design Paradigm To Improve Verification Efficiency
By Harry Foster - 10 Mar, 2022 - Comments: 0

We are in the midst of a verification crisis manifested by a growing gap between verification efficiency and effectiveness. This crisis cannot be solved through improvements in verification methodologies and techniques alone. Indeed, it requires a philosophical change in the way we approach design, with an emphasis on bug prevention. We refer to this fundamental change as design using intent-fo... » read more

Accelerating Verification Shift Left With Intelligent Coverage Optimization
By Synopsys - 12 Oct, 2021 - Comments: 0

Functional verification dominates semiconductor development, consuming the largest percentage of project time and resources. Team members look at the rate of design bug discovery, consider anecdotal information on the types of bugs that escaped to silicon in previous projects, and use their best judgment based on their years of experience to determine when to tape out. Above all, they look at v... » read more

A Methodology To Verify Functionality, Security, And Trust for RISC-V Cores
By OneSpin Solutions - 28 Jul, 2021 - Comments: 0

Modern processor designs present some of the toughest hardware verification challenges. These challenges are especially acute for RISC-V processor core designs, with a wide range of variations and implementations available from a plethora of sources. This paper describes a verification methodology available to both RISC-V core providers and system-on-chip (SoC) teams integrating these cores. It... » read more

ASIC/IC Verification Trends With A Focus On Factors Of Silicon Success
By Harry Foster - 08 Jul, 2021 - Comments: 0

At long last we come to the final installment of our four-part series presenting the findings of the Wilson Research Group Functional Verification 2020 study. In this article we discuss verification trends in IC/ASIC language and library adoption, low power management, and verification effectiveness. We then take a deeper dive into two somewhat surprising phenomena revealed in the data: the ... » read more

Beyond The Water Cooler: 2020 Report On IC/ASIC Design And Verification Trends
By Harry Foster - 10 Jun, 2021 - Comments: 0

Verification and design engineers like to talk shop and discuss their experiences and visions. But even though engineers sharing stories around the water cooler (whatever form that takes—conferences, blogs, etc.) does provide all kinds of valuable insights, it doesn’t provide the full picture into the very large and complicated and extremely dynamic global semiconductor industry. To better ... » read more

Verification Effectiveness In The Face Of FPGA Complexity: The 2020 Wilson Research Group Functional Verification Study
By Harry Foster - 08 Apr, 2021 - Comments: 0

Making informed decisions backed by good data is the key to success in highly competitive, robust markets such as FPGA design and verification. Helping our community in that endeavor is the motivation behind the worldwide Wilson Research Group Functional Verification Study. We also use that information to make sure our research and development efforts continue to deliver the solutions our cu... » read more

Accelerating SoC Verification Closure With Unified Verification Management Solution
By Synopsys - 08 Feb, 2021 - Comments: 0

Functional verification of system-on-chip (SoC) designs requires best-in-class tools linked together in a unified solution in order to address exponential complexity challenges. There is no one-size-fits-all method for verification. Complex designs require a combination of virtual prototyping, static checks, formal analysis, simulation, emulation and FPGA prototyping. The execution of all the t... » read more

Importance Of A Functional Verification Methodology
By Shubhodeep Roy Choudhury - 24 Sep, 2020 - Comments: 0

A good functional verification methodology is extremely crucial to the success of any semiconductor design project. Missed or late bugs can massively hurt market share, revenue, and brand name even for reputed companies. The complexity of SoC designs along with tight time-to-market constraints demand high levels of efficiency in the verification process. The approach to verify the functional... » read more

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