Chip Industry Week In Review


Micron The memory maker rolled out a slew of announcements this week, including: Raised its planned U.S. investment to more than $250B through 2035, an incremental $50B above what was announced last June, with an ultimate goal of producing 40% of its DRAM in the U.S.; Planned new investments of $3B for U.S. IC supply-chain investments, including $500M in financing for GlobalWafers’ 3... » read more

Where Does Quantum Computing Stand?


Key Takeaways:  Quantum technology is seeing very active development, but most commercial offerings remain years away.  QED-C represents the industry and provides reports and roadmaps.  The three main elements that need definition are the qubit, error correction, and software, both for control and for algorithms.  Quantum computing has imprinted itself on our society as ... » read more

Chip Industry Week In Review


Around the world South Korea unveiled a sweeping AI and semiconductor investment drive, planning three mega projects that tie semiconductors, physical AI/robotics, and AI data centers into a single industrial plan, with government support for regional chip clusters, packaging capacity, power, water, sites, and workforce development. Among the new investments: Samsung will spend $260B on n... » read more

Chip Industry Week In Review


IBM unveiled a 7Å transistor architecture that uses staggered nanosheet transistors stacked on a precisely beveled angle, almost like tiles on a roof. That allows more transistors to be crammed into a given area, boosting performance by 50% or power efficiency by up to 70%. Perhaps even more important, IBM claims a 40% improvement in SRAM scaling, which is orders of magnitude faster and lower ... » read more

Chip Industry Week In Review


Computex in Taiwan: Arm and Nvidia introduced an AI PC platform, RTX Spark, with an Arm-based Grace CPU, Blackwell RTX GPU, and unified memory. Cadence announced a fully autonomous virtual agentic AI design engineer, enabling customers to run dynamic simulations in automated workflows. Intel launched Xeon 6+, its first data-center CPU built on Intel Foundry's 18A process. The company... » read more

Chip Industry Week In Review


ECTC Panel-level packaging, hybrid bonding, new substrates, and fine-pitch interconnects topped the list of advanced packaging technologies at ECTC this week. Among the announcements: ASE launched an automated 310mm × 310mm panel-level packaging production line. Expected to enter production in the first half of 2027, the line is compatible with FOCoS and FOCoS-Bridge pa... » read more

Chip Industry Week In Review


Advanced nodes and packaging AMD announced more than $10B in Taiwan ecosystem investments to scale advanced packaging manufacturing for AI infrastructure. The effort includes EFB-based 2.5D packaging collaborations with ASE and others. AMD also announced the start of its production ramp of its Venice processors on TSMC's 2nm process. Lam Research established a panel-level packaging cen... » read more

Low-Temp Solders Are Suddenly Critical For Chiplets And Photonics


Key Takeaways: Tin-bismuth-based solders enable reduced warpage and compatibility with silicon photonics and other temperature-sensitive components. A novel soldering process using white light could help prevent cracks in flip-chip BGA package solder balls, while reducing the carbon footprint. Hypoeutectic Sn-Bi based solders prove especially promising as an SAC305 replacement. ... » read more

Scalable Photomask Optimization With Morphological Learning (SUNY Buffalo, VU, IBM)


A new technical paper, "MorphOPC: Advancing Mask Optimization with Multi-scale Hierarchical Morphological Learning," was published by researchers at University at Buffalo, Villanova University, and IBM T. J. Watson Research Center. Abstract "As feature sizes shrink to the nanometer scale, accurately transferring circuit patterns from photomasks to silicon wafers becomes increasingly chall... » read more

GPU Power Prediction Tool for AI Workloads (MIT, IBM)


A new technical paper, "EnergAIzer: Fast and Accurate GPU Power Estimation Framework for AI Workloads," was published by researchers at MIT and IBM Research. Abstract "As AI workloads drive increases in datacenter power consumption, accurate GPU power estimation is critical for proactive power management. However, existing power models face a scalability bottleneck not in the modeling tec... » read more

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