tag: IBM

New Issues In Signoff
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling Signoff has always been a challenge at every stage of an SoC design flow. No matter how good a design looks, or how well a prototype works, there are still problems that can crop up at any stage of the design flow all the way into manufacturing that can leave engineering teams shaking their heads. Even at mainstream process nodes, respins are common. At advanced nodes—part... » read more

Uncommon Goals
By Atrenta - 14 Feb, 2013 - Comments: 0

I had the opportunity to attend the Common Platform event recently. This is a technology and business showcase sponsored by Global Foundries, IBM and Samsung with major support from ARM, Cadence, Synopsys and Mentor. Wow, that’s some serious sponsorship. The event was well run and provided a good balance of technology details and business outlook. The wine at the evening reception was decent ... » read more

Tech Talk: Getting To The Next Node
By Ed Sperling - 14 Feb, 2013 - Comments: 0

IBM's Gary Patton talks with Low-Power/High-Performance Engineering about finFETs, EUV, and the challenges of staying on the Moore's Law road map. [youtube vid=jtz9XSXyBp0] » read more

Math Questions
By Ed Sperling - 08 Feb, 2013 - Comments: 0

The race is on. GlobalFoundries, TSMC, Samsung, IBM and Intel are all neck deep in research, test chips, variability, lithography and three-dimensional transistor designs. For the first time, though, the goal very publicly has shifted from performance and area to energy efficiency. Being able to double battery life with existing performance over the next couple nodes could mean smart phones ... » read more

What Will Replace Dual Damascene?
By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus In the mid-1990s, IBM announced the world’s first devices using a copper dual damascene process. At the time, the dual damascene manufacturing process was hailed as a major breakthrough. The new copper process enabled IC makers to scale the tiny interconnects in a device, as the previous material, aluminum, faced some major limitations. Dual damascene remains the workhorse... » read more

Lessons From Past Architecture Wars
By Marc David Levenson - 24 Jan, 2013 - Comments: 0

By Marc David Levenson There was an interesting IEEE panel discussion in Silicon Valley recently, reviewing the microprocessor architecture wars of the ’70s, ’80s and ’90s. How did the Intel x86 architecture become so dominant when there were other capable designs, including more efficient RISC (Reduced Instruction Set Computing) chips? How did the x86s overcome competition from Zilog, M... » read more

Tradeoffs On The Fly
By Ed Sperling - 17 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler With classical bulk planar technology no longer shrinkable, the industry has been honing in on new ways to continue some scaling, achieve extra speed or better power while minimizing leakage. “To overcome the limits [of bulk planar technology] we need a different solution,” explained Giorgio Cesano, technology R&D marketing director at STMicroelectron... » read more

Shaking Up The Green500
By Barry Pangrle - 17 Jan, 2013 - Comments: 0

Barry Pangrle Last September, I wrote about the efficiency of IBM’s Power7+ architecture in my blog. IBM’s Sequoia supercomputer (a BlueGene/Q system) this past June had just shot to the top of the Supercomputing Top500 chart, clocking in at 16.32 petaflop/s on the Linpack benchmark. Other systems built around the IBM BlueGene/Q, Power BQC 16C 1.60GHz, Custom were also dominating the top o... » read more

Foundry Landscape Changes In 3D
By Mark LaPedus - 13 Dec, 2012 - Comments: 0

By Mark LaPedus Over the last year, leading-edge silicon foundries announced their new and respective strategies in the emerging 2.5D/3D chip arena. The ink is barely dry and now the foundry landscape is changing. One new vendor, Tezzaron Semiconductor, is entering the market. The 3D DRAM supplier plans to provide select 2.5D/3D foundry services within its recently acquired fab in Austin, T... » read more

Upping The Ante
By Ed Sperling - 13 Dec, 2012 - Comments: 0

The increasing number of research projects under way to solve many of the thorniest issues in the history of semiconductor design and manufacturing are a testament to just how tough the job has become. Never before have there been so many technological roadblocks at the same time—and so many potential options for solving them. Those challenges—or opportunities, as marketing execs like to... » read more

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