The Bumpy Road To 450mm

Progress has been made, but there’s still a lot of work to do over the next five years if the industry expects to meet its 2018 rollout schedule; economic benefits still being discussed.


By Mark LaPedus
After its formation nearly 20 months ago, a 450mm consortium has reached its latest milestone by recently completing a cleanroom and installing the first 450mm demonstration tools in the facility.

The so-called Global 450 Consortium (G450C) also has set a goal to bring 450mm fabs into high-volume manufacturing at the 10nm or 7nm nodes by 2018. That gives the industry a little less than five years to develop the production tools for 450mm fabs, which are expected to cost a whopping $10 billion or more. Based in Albany, N.Y., the G450C has five members—GlobalFoundries, Intel, IBM, Samsung and TSMC.

But between now and 2018, there is a staggering amount of work to be done. Based on the current progress for select equipment, fab technologies and standards, the path towards 450mm will be a bumpy road and it’s unclear if the industry can meet the 2018 target.

The most obvious problem is lithography. For example, ASML Holding is not expected to deliver a production-worthy, 450mm version of its extreme ultraviolet (EUV) lithography scanner until 2018. Other challenges include lithographic cost-of-ownership and throughput.

On the wafer-processing front, Applied, Lam, TEL and others are moving full speed ahead in 450mm. TEL also is proposing an “open platform” standard—a move that has received a lukewarm response. Meanwhile, there is some movement in metrology, as a new consortium has recently been formed to address the challenges in 450mm.

And the industry is still debating over various 450mm fab standards, such as aisle space and ceiling height. There is even a debate over the type of cranes needed to install 450mm tools. Other standards, such as gas interface boxes, cooling water manifolds, and hookups for power, are also in the works.

That’s just the tip of the iceberg. The goal for the G450C is not only to help develop these technologies, but it also has the arduous task of getting the various players to synchronize on the roadmap. “It’s going to require a collaborative and concerted effort to introduce (450mm technology) in an efficient manner,” said Steve Johnston, director of external programs and technology strategy in the Technology Manufacturing Engineering Group at Intel, at a recent SEMI event. “All of this requires flawless and synchronized execution across the industry and at multiple levels.”

Avoiding past mistakes
Indeed, the industry hopes to avoid past mistakes. In the mid-1990s, the IC industry wanted to make the shift from 200mm to 300mm fabs. The equipment industry had the 300mm tools ready in the late 1990s, but chipmakers pushed out their 300mm fabs amid an IC downturn. Equipment vendors ended up holding the bag and lost a fortune. Shortly thereafter, chipmakers began to ramp up their 300mm fabs, but the events left a bad taste in vendors’ mouths.

Recently, Intel, Samsung and TSMC have been pushing for 450mm fabs. The argument is that the industry needs to make a wafer transition every 15 years to stay on Moore’s Law. Moving to 450mm wafers will give chipmakers a 2.25x boost in wafer area and a 30% cost reduction, according to chipmakers.

For some time, however, fab tool vendors were lukewarm about 450mm. There are only a handful of customers who would buy 450mm tools, and it’s unclear who will foot the R&D bill for the technology.

More recently, 450mm has become a reality. Intel and TSMC have outlined plans to build 450mm fabs. And in 2011, the G450C was established at the College of Nanoscale Science and Engineering’s NanoTech Complex. The G450C recently opened a cleanroom. Its roadmap also calls for 450mm pilot lines in 2015 and 2016, with high-volume production targeted for 2018.

“Synchronization and collaboration are very important to avoid the same type of issues we ran into in the late 1990s with the transition to 300mm,” said Kirk Hasserjian, corporate vice president for the Silicon Systems Group at Applied Materials.

There are other issues, namely supply-chain readiness, return-on-investment and R&D funding. “The (R&D funding) issue requires a very different business model,” Hasserjian said. “That has not been completely resolved. We have the consortium activities, which have provided some level of funding.”

Fab tool challenges
The industry has moved to fund at least one technology, namely lithography. Intel, Samsung and TSMC recently invested in ASML, in an effort to accelerate ASML’s efforts in 450mm and EUV. And with separate funding from Intel, Nikon is developing a 193nm immersion scanner for 450mm.

ASML itself has initiated 450mm programs on two separate platforms and four wavelengths, including EUV. The goal is to deliver “early version tools” in 2015 to 2016, with 450mm production systems due out by 2018, said Jim Koonmen, general manager of Brion Technologies, a division of ASML.

The development of a 450mm EUV scanner is expected to be a herculean effort. Today, ASML is struggling to deliver 300mm EUV tools amid delays with the power sources. Cost is also an issue, as ASML’s pre-production EUV scanners cost $100 million or more per unit today.

Throughput is also an issue. The throughput for a 450mm scanner in general is projected to be only about one-half of a 300mm tool, Koonmen said. A 300mm tool has a throughput of about 250 wafers per hour (wph), while a 450mm system can run 100-125 wph at 1.1x the cost, he said.

“If you look at the entire semiconductor process, there are steps that do get a lot of leverage from larger wafer sizes and can realize cost reduction,” he said. “Unfortunately, with lithography, there simply isn’t that much of a benefit in going to larger wafer sizes. We are scanning as fast as we can. The number of fields is going to increase when we go to larger wafers, but that just means your throughput for each 450mm wafer is going to go down. So you’ve got double the number of fields, but you are going at half the throughput. That in itself is not easy to do. In order to handle a 450mm wafer, you need to have larger stages with larger masks, and that creates a whole bunch of issues for us.”

Meanwhile, amid the problems with EUV, the industry is hedging its bets by developing 193nm immersion scanners for 450mm. Optical is a proven technology, but the solution is expensive. At 10nm or 7nm, chipmakers must also use expensive multiple patterning schemes.

Delivery schedules for 193nm immersion are more certain, however. “450mm is expected to be in production by 2018,” said Hamid Zarringhalam, executive vice president at Nikon Precision. “We will ship development tools earlier than that.” By 2015, Nikon plans to ship “early learning tools” based on 193nm immersion for 450mm, Zarringhalam said. Nikon has already garnered “multiple orders” for the systems, he added.

On the wafer processing side, there are also some technical and cost challenges. “Prices could rise 30% to 50% for 450mm tools, as they did when the wafer size shifted to 300mm from 200mm,” said analyst David Motozo Rubenstein, who is also the author of a blog entitled “Chips and Dips.”

Applied, Lam, TEL and others are developing standalone 450mm tools. TEL also is proposing the idea of having an “open and modular platform” for 450mm. This would enable fab tool vendors to develop various plug-and-play process modules for the open platform, thereby reducing costs and development times. TEL and its rivals could develop modules for the platform. “The open platform is a concept for the 450mm high-volume manufacturing era,” said Aki Sekiguchi, vice president and general manager for SPE marketing at TEL.

The open platform could benefit smaller companies that don’t have the resources to develop standalone tools. But larger companies are not eager to endorse an open platform, because it will give its rivals a competitive edge. “We are looking at it,” said Applied’s Hasserjian. “We are not doing what TEL is doing and advocating a modular platform.”

Metrology challenges

Another challenge is the development of 450mm metrology gear. “There are not many companies that can invest six years in advance,” said Menachem Shoval, chairman of Metro450, an Israeli-based consortium that is developing 450mm metrology technology. “Even without going 450mm, there are huge challenges for metrology in terms of going down from 22nm to 14nm to 10nm to 7nm.”

This is especially true when moving from today’s planar devices to finFETs at 22nm and beyond. “Going to 3D has created numerous challenges for us,” said John Allgair, senior member of the technical staff at GlobalFoundries. “We see tenfold measurement problems as we go to 3D. A lot of things you see in 2D tend to get amplified as we go to these 3D structures. Then, we see some real challenges when it comes to compositional analysis. In finFET devices, we’ve got compositional measurements like SiGe with a percentage of germanium and a percentage of boron on a 3D structure. That’s a very complex measurement. Finally, we try and do measurements on test structures. The test structures don’t always mimic what’s actually taking place on your device. That really adds to the complexity of trying to manufacture finFETs in a stable manner.”

One solution to the problem is to collaborate through a consortium, Metro450’s Shoval said. Last year, for example, the Metro450 consortium was formed by the following companies—Applied Materials, Nova, Jordan Valley, Nanomotion and Intel. The group also consists of four universities in Israel, with some 60% of the funding coming from the Israeli government.

“Each company develops its own technology,” Shoval said. “They are competing with each other. But we can collaborate on those parts which are common. We will work on platforms, but not on detection.”

One of the goals for the Metro450 group is to meet the design rule targets by 2017. It is also devising technologies that are 2.5x faster than 300mm, thereby meeting the cost requirements for 450mm. To reach its goals, the group is working on five specific technologies: wafer handling; sampling optimization; wafer damage and contamination; calibration; and data processing.

“We plan to complete our work in three years,” Shoval said. “So companies will still have about three years to complete the development of their high-volume manufacturing tools.”

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