tag: IP

Waiting For Chiplet Interfaces
By Brian Bailey - 13 Jun, 2019 - Comments: 0

There aren't many success stories related to chiplets today for a very simple reason—there are few standard interfaces defined for how to connect them. In fact, the only way to use them is to control both sides of the interface with a proprietary interface and protocol. The one exception is the definition of HBM2, which enables large quantities of third-party DRAM to be connected to a logi... » read more

BiST Grows Up In Automotive
By Ann Mutschler - 12 Jun, 2019 - Comments: 0

Test concepts and methods that have been used for many years in traditional semiconductor and SoC design are now being leveraged for automotive chips, but they need to be adapted and upgraded to enable monitoring of advanced automotive systems during operation of a vehicle. Automotive and safety critical designs have very high quality, reliability, and safety requirements, which pairs pe... » read more

How To Meet Power Performance And Cost for Autonomous Vehicle Systems Using Speedcore eFPGAs
By Achronix - 05 Jun, 2019 - Comments: 0

In the advanced, fully autonomous, self-driving vehicles of the future, the existence of dozens and even hundreds of distributed CPUs and numerous other processing elements is assured. Peripheral sensor-fusion and other processing tasks can be served by ASICs, SoCs, or traditional FPGAs. But the introduction of embedded FPGA blocks such as Achronix's Speedcore eFPGA IP provides numerous system-... » read more

Using Synopsys Z01X To Accelerate The Fault Injection Campaign Of A Fully Configurable IP
By Arteris - 05 Jun, 2019 - Comments: 0

By Arteris IP Alexis Boutillier, Corporate Application Manager, Safety Manager, and Mohan Krishnareddy, Solution Engineer, at the Synopsys Users Group (SNUG), March 2018, Santa Clara, CA. Principles and real-world practices of ISO 26262 for semiconductor design teams. After providing an overview of how functional safety affects management, development, and supporting processes, the paper exp... » read more

CEO Outlook: It Gets Much Harder From Here
By Ed Sperling - 03 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

Moore Open Source Coming
By Brian Bailey - 30 May, 2019 - Comments: 0

The sunsetting of Moore's Law is creating some interesting ripples throughout the EDA and IP industries. No longer is the low-risk path defined by a migration to the next node. Most companies cannot afford it and don’t need it. Neither can their competitors. Suddenly, they have to do more with less, or at least the same amount. Consider just a few things that are changing today: Stick... » read more

Intellectual Property: Trust… But Verify
By John Hallman - 30 May, 2019 - Comments: 0

For those around the microelectronic component industry for many years, we have seen quite a transformation of capability, sourcing of the supply chain, and now threats to these devices that drive the technology in our world today. These integrated circuits (ICs), once so simple as a few transistors, have continued to follow Moore’s Law and are now made up of tens of billions of transistor... » read more

Why IP Quality Is So Difficult To Determine
By Ann Mutschler - 30 May, 2019 - Comments: 0

Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends up on how and where it is used and in part because even the best IP may work better in one system than another—even in chips developed by the same vendor. This has been one of the challenges with IP over the years. In many cases, IP is poorly characterized, regardless of whether that IP wa... » read more

Evolution Of Verification Engineers
By Brian Bailey - 22 May, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions archit... » read more

In-Chip Monitoring Becoming Essential Below 10nm
By Ann Mutschler - 20 May, 2019 - Comments: 0

Rising systemic complexity and more potential interactions in heterogeneous designs is making it much more difficult to ensure a chip, or even a block within a chip, will functioning properly without actually monitoring that behavior in real-time. Continuous and sporadic monitoring have been creeping into designs for the past couple of decades. But it hasn’t always been clear how effective... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy