tag: IP

High-Performance 7nm IP Verification With The AFS Platform At Silicon Creations
By Mentor, a Siemens Business - 29 Nov, 2017 - Comments: 0

While there are many benefits to migrating to smaller process geometries, such as lower power and higher performance, the increased design complexity places an even higher burden on fast and efficient simulation technology. In addition, fast and accurate resistor/capacitor (RC) extraction is becoming increasingly important. Interconnect resistance is an increasing percentage of the total path r... » read more

New Drivers For I/O
By Brian Bailey - 13 Nov, 2017 - Comments: 0

Interface standards are on a tear, and new markets are pushing the standards in several directions at the same time. The result could be a lot more innovation and some updates in areas that looked to be well established. Traditionally, this has been a sleepy and predictable part of the industry with standards bodies producing updates to their interfaces at a reasonable rate. Getting data int... » read more

Mixed Messages For Mixed-Signal
By Brian Bailey - 09 Nov, 2017 - Comments: 1

There is no such thing as a purely digital design at advanced nodes today. Even designs that have no [getkc id="37" kc_name="analog"] content are likely relying on [getkc id="38" kc_name="mixed-signal"] components such as SerDes for communications, or voltage regulators for adaptive power control. But the days of purposely attempting to integrate everything including analog and RF onto a single... » read more

Effective Management Of System Designs
By Ranjit Adhikary - 08 Nov, 2017 - Comments: 0

With the advent of the Internet-of-Things (IoT), system designs are slowly but surely becoming more complex. They now use heterogeneous architectures both on the System-on-Chip (SoC) and within a package. These systems typically have multiple different CPU cores, hardware accelerators, memories, network-on-chip (NoC) fabrics and numerous peripheral interfaces. Now, add to this the complexiti... » read more

Chiplets Gaining Steam
By Ann Mutschler - 06 Nov, 2017 - Comments: 0

Building chips from pre-verified chiplets is beginning to gain traction as a way of cutting costs and reducing time to market for heterogeneous designs. The chiplet concept has been on the drawing board for some time, but it has been viewed more as a possible future direction than a necessary solution. That perception is beginning to change as complexity rises, particularly at advanced nodes... » read more

STMicroelectronics’ Implementation Of The STAR Hierarchical System And IEEE 1500 Wrapping
By Synopsys - 01 Nov, 2017 - Comments: 0

This white paper discusses various IEEE 1500 architectures that STMicroelectronics has deployed using the Synopsys DesignWare STAR Hierarchical System test solution. STAR Hierarchical System allows users to optimize test time on system-on-chips that use multiple cores. The white paper provides guidelines on interface IP wrapping with IEEE 1500 to improve test time. In addition, it discusses the... » read more

Which Verification Engine?
By Ed Sperling - 01 Nov, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

Dealing With Deadlocks
By Ann Mutschler - 26 Oct, 2017 - Comments: 1

Deadlocks are becoming increasingly problematic as designs becoming more complex and heterogeneous. Rather than just integrating IP, the challenge is understanding all of the possible interactions and dependencies. That affects the choice of IP, how it is implemented in a design, and how it is verified. And it adds a whole bunch of unknowns into an already complex formula for return on inves... » read more

Securing High-Value Embedded Targets
By Rich Collins - 12 Oct, 2017 - Comments: 0

Understanding security threats and building solutions to protect against them is a relatively new concept for embedded developers. As an example, many early IoT devices were focused purely on cost. Designers spent very little time architecting robust security solutions. Today, these devices are more involved in users’ daily routines, processing sensitive data such as personal medical informat... » read more

Trimming Waste In Chips
By Brian Bailey - 12 Oct, 2017 - Comments: 0

Extra circuitry costs money, reduces performance and increases power consumption. But how much can really be trimmed? When people are asked that question they either get defensive or they see it as an opportunity to show the advantages of their architecture, design process or IP. The same holds true for IP suppliers. Others point out that the whole concept of waste is somewhat strange, becau... » read more

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