Tech Talk: IP Integration Part 2


Sonics CTO Drew Wingard talks about the challenges of integrating IP into SoCs in this second of two parts. [youtube vid=ipQkPjJMcgY] » read more

Are Models Holding Back New Methodologies


Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="101" kc_name="modeling"] at abstractions above [getkc id="49" kc_name="RTL"], a factor which has delayed adoption of [getkc id="104" kn_name="virtual prototypes"] and the proliferation of system-level design and hardware/software codesign. Taking part in the discussion were Frank Schirmeister, group director,... » read more

Tech Talk: SW vs. HW


Arteris CTO Craig Forest talks about what gets done in hardware, what gets done in software, and where the two worlds meet and sometimes collide. [youtube vid=-EbUTZL0uz8] » read more

Securing The IoT


Semiconductor Engineering sat down to discuss whether the [getkc id="76" comment="Internet of Things"] will be secure enough, or whether it will create new security issues, with Sami Nassar, general manager of [getentity id="22499" comment="NXP Semiconductor"]; Oleg Logvinov, director for special assignments at [getentity id="22331" comment="STMicroelectronics"]; and Lawrence Loh, application e... » read more

Week 19: Ready. Steady. Go!


The window for submitting to the IP and designer tracks opens on Oct. 23. It’s time to get ready and check with your management if you can present your work at DAC. You can find the submission details and a link to last year’s content here. You can even browse presentation examples from past designer tracks. If you are an EDA vendor, the designer track is a good opportunity for your use... » read more

The Week In Review: Design


Legal Mentor Graphics won a $36 million award plus royalties stemming from a patent infringement case involving EVE (Emulation & Verification Engineering), an emulation company that was purchased by Synopsys in 2012. A U.S. District Court jury in the District of Oregon found that EVE had directly and indirectly infringed on a 2001 patent entitled "Method and apparatus for gate-level simula... » read more

The Week In Review: Design


IP Synopsys rolled out verification IP for mobile PCIe, including built-in M-PHY, for UVM environments. Cadence introduced MIPI SoundWire controller IP, which allows bi-directional digital communication using low gate count and minimal complexity. Deals ARM and TSMC rolled out a road map for 64-bit ARM-based processors at 10nm. The companies said the early pathfinding work is expected t... » read more

Optimizing Analog For Power At Advanced Nodes


As any engineering manager will tell you, analog and digital engineers seem like they could be from different planets. While this has changed somewhat over time, [getkc id="52" comment="analog"] is still something of a mystery to many in [getkc id="81" kc_name="SoC"] design teams. Throw power management into the mix and things really get interesting. Improvements in analog/mixed-signal tools... » read more

Memory VIP


As the consumer market, and the mobile segment in particular, continues to demand more features and more performance in their gadgets, the designer community is confronted with myriad challenges of delivering on those demands – not the least of which is verifying compliance of ever-evolving protocols that enable the connection of everything within the system on chip (SoC), and the connection ... » read more

Taking The Mystery Out Of IP, SoC And Automotive System Debug


I recently had to take my car to the dealership because the gas-saving "auto-shut-off-while-stopped" feature wasn't working. The dealer explained that the reason it took two days to debug was because it "touched on many systems" in the car. In the end, they realized the battery wasn't fully charged and blamed it on my short 10-mile commute. Whether that was an honest answer or an example of ... » read more

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