The Week In Review: Design

MIPI IP; preparing for 10nm processors; Synopsys inks deal with HiSilicon; Cadence to sell $350M in notes; Intel CSO warns about data use and accountability.


Synopsys rolled out verification IP for mobile PCIe, including built-in M-PHY, for UVM environments.

Cadence introduced MIPI SoundWire controller IP, which allows bi-directional digital communication using low gate count and minimal complexity.

ARM and TSMC rolled out a road map for 64-bit ARM-based processors at 10nm. The companies said the early pathfinding work is expected to yield tapeouts starting Q4 of next year.

Synopsys won a deal with China’s HiSilicon, which will use Synopsys’ signoff and timing closure tool in finFET designs.

Cadence will offer $350 million in unsecured notes bearing interest of 4.375% per year. The company plans to use the money for general corporate purposes, including retiring of debt.

Intel‘s chief security and privacy officer, Malcolm Harkins, urged a group of leaders in technology, healthcare and other fields to be more open and accountable when collecting and using consumer data. Citing a Harris Poll, Harkins said a fear about how that data is used could have a bad effect on progress—and business.

DVCon Europe will be held in Munich on Oct. 14 – 15.

Memcon will be held on Oct. 15 in the Santa Clara Convention Center.

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