tag: interconnect

A review of interconnect materials used in emerging memory device packaging: first- and second-level interconnect materials
By Technical Paper Link - 23 Dec, 2021 - Comments: 0

Abstract "The main motivation of this review is to study the evolution of first and second level of interconnect materials used in memory device semiconductor packaging. Evolutions of bonding wires from gold (Au) to silver (Ag) or copper (Cu) have been reported and studied in previous literatures for low-cost solution, but Au wire still gives highest rating in terms of the performance of tempe... » read more

NoC Experiences From The Trenches
By Kurt Shuler - 28 Sep, 2021 - Comments: 0

Network-on-chip (NoC) interconnect as an alternative to traditional crossbars is already well-proven, but there are still plenty of design teams on the cusp of a transition or who maybe do not yet see a need for a change. As with a switch to any new technology, the first hurdles are often simply misconceptions. When new users first evaluate any new technology, they often make the mistake of att... » read more

Advancing To The 3nm Node And Beyond: Technology, Challenges And Solutions
By Michael Hargrove - 19 Aug, 2021 - Comments: 0

It seems like yesterday that finFETs were the answer to device scaling limitations imposed by shrinking gate lengths and required electrostatics. The introduction of finFETs began at the 22nm node and has continued through the 7nm node. Beyond 7nm, it looks like nanosheet device structures will be used for at least the 5nm and probably the 3nm nodes. The nanosheet device structure is the brainc... » read more

SoC Integration Complexity: Size Doesn’t (Always) Matter
By Kurt Shuler - 01 Apr, 2021 - Comments: 2

It’s common when talking about complexity in systems-on-chip (SoCs) to haul out monster examples: application processors, giant AI chips, and the like. Breaking with that tradition, consider an internet of things (IoT) design, which can still challenge engineers with plenty of complexity in architecture and integration. This complexity springs from two drivers: very low power consumption, eve... » read more

CXL: Sorting Out The Interconnect Soup
By Tim Messegee - 11 Feb, 2021 - Comments: 0

In the webinar Hidden Signals: Memory and Interconnect Decisions for AI, IoT and 5G, Shane Rau of IDC and Rambus Fellow Steven Woo discussed how interconnects were a critical enabling technology for future computing platforms. One of the major complications was the “interconnect soup” of numerous and divergent interface protocols. The Compute Express Link (CXL) standard offers to sort out m... » read more

Die-To-Die Stress Becomes A Major Issue
By Ann Mutschler - 14 Jan, 2021 - Comments: 2

Stress is becoming more critical to identify and plan for at advanced nodes and in advanced packages, where a simple mismatch can impact performance, power, and the reliability of a device throughout its projected lifetime. In the past, the chip, package, and board in a system generally were designed separately and connected through interfaces from the die to the package, and from the packag... » read more

The Role Of NoCs In System-Level Services
By Kurt Shuler - 03 Sep, 2020 - Comments: 0

The primary objective of any network-on-chip (NoC) interconnect is to move data around a chip as efficiently as possible with as little impact as possible on design closure while meeting or exceeding key design metrics (PPA, etc.). These networks have become the central nervous system of SoCs and are starting to play a larger role in system-level services like quality of service (QoS), debug, p... » read more

Better Analytics Needed For Assembly
By Anne Meixner - 11 Aug, 2020 - Comments: 0

Package equipment sensors, newer inspection techniques, and analytics enable quality and yield improvement, but all of those will require a bigger investment on the part of assembly houses. That's easier said than done. Assembly operations long have operated on thin profit margins because their tasks were considered easy to manage. Much has changed over the past several years, however. The r... » read more

Interconnect Challenges Grow, Tools Lag
By Brian Bailey - 15 Jun, 2020 - Comments: 2

Interconnects are becoming much more problematic as devices shrink and the amount of data being moved around a system continues to rise. This limitation has shown up several times in the past, and it's happening again today. But when the interconnect becomes an issue, it cannot be solved in the same way issues are solved for other aspects of a chip. Typically it results in disruption in how ... » read more

eFPGA As Fast And Dense As FPGA, On Any Process Node
By Geoff Tate - 04 Jun, 2020 - Comments: 0

A challenge for eFPGA when we started Flex Logix is that there are many customers and applications, and they all seemed to want eFPGA on different foundries, different nodes and different array sizes. And everyone wanted the eFPGA to be as fast and as dense as FPGA leaders’ on the same node. Oh, and customers seem to wait to the last minute then need the eFPGA ASAP. Xilinx and Altera (Intel ... » read more

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