tag: interconnect

The Week In Review: Design
By Ed Sperling - 27 Jun, 2014 - Comments: 0

Tools eSilicon uncorked a GDSII online quote system for TSMC, which allows chipmakers to pick a variety of information ranging from process technology to package to yield and tapeout and production forecast and get a quote within minutes. This is a new twist in the value chain provider market. Synopsys added program to speed up FPGA-based prototype creation, which includes approved third-pa... » read more

Locking Down The Chip
By Ernest Worthman - 05 Jun, 2014 - Comments: 1

The crypto processor is poised to break into the mainstream SoC world. Lower costs for manufacturing, coupled with rising security concerns from increased connectivity and growing complexity have cracked open the door on this approach to locking down a chip. Crypto processors aren’t a new concept, but they generally have been reserved for high-end applications. Until recently, they have ju... » read more

Manufacturing Bits: June 3
By Mark LaPedus - 03 Jun, 2014 - Comments: 0

World’s thinnest TFTs The U.S. Department of Energy’s Argonne National Laboratory has devised the world’s thinnest flexible, 2D thin-film transistors (TFTs). The transistors are just 10 atomic layers thick. TFTs are typically used in screens and displays. In the lab, Argonne researchers fabricated the TFTs on both a conventional silicon platform and a flexible substrate. [caption i... » read more

Executive Insight: Charles Janac
By Ed Sperling - 30 May, 2014 - Comments: 0

SE: What’s your biggest concern? Janac: Staying current. One of the things that is really important is to understand shifts in the marketplace. In the past, we looked at whether to target our interconnect solution at digital TV or mobility. This was actually a very interesting question in 2005. The DTV market looked better, but we were not getting enough evaluations. We were doing better i... » read more

Manufacturing Bits: May 27
By Mark LaPedus - 27 May, 2014 - Comments: 0

Chip printing process Fraunhofer Institute for Manufacturing Technology and Advanced Materials has developed a novel way to make systems using electronic components, such as resistors, transistors and capacitors. Researchers use simple printers and a robot-assisted production line. The components and other devices made from the technology could be used in various applications, such as digit... » read more

Cobalt To The Rescue
By Mark LaPedus - 13 May, 2014 - Comments: 0

A big concern for chipmakers is a key part of the manufacturing flow—the backend-of-the-line (BEOL). In chip production, the BEOL is where the interconnects are formed within a device. Interconnects, those tiny wiring schemes in devices, are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the dreaded resistance-capacitance (RC) ... » read more

3D IC Supply Chain: Still Under Construction
By Barbara Jorgensen - 25 Jul, 2013 - Comments: 1

By Barbara Jorgensen and Ed Sperling Stacked die, which promise high levels of integration, a tiny footprint, energy conservation and blinding speed, still have some big hurdles to overcome. Cost, packaging and manufacturability continue to make steady progress, with test chips being produced by all of the major foundries. But in a disaggregated ecosystem, the supply chain remains a big st... » read more

Just Add IP
By Kurt Shuler - 30 May, 2013 - Comments: 0

When discussing SoC design with my semiconductor design and software development peers, the conversation eventually gets around to the problem of, “There’s just too much IP!” The feelings I hear border on exasperation at the problem of integrating IP on today’s large SoCs. Engineers who were once paid to write lines of Verilog or C code from scratch are now spending much of their time t... » read more

Challenges Mount For Interconnect
By Mark LaPedus - 26 Jun, 2012 - Comments: 0

By Mark LaPedus There are a plethora of chip-manufacturing challenges for the 20nm node and beyond. When asked what are the top challenges facing leading-edge chip makers today, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, said it boils down to two major hurdles: lithography and the interconnect. The problems with lithography are well documented.... » read more

Interconnect Power
By Barry Pangrle - 11 Aug, 2011 - Comments: 0

By Barry Pangrle Applied Materials announced its latest version of nano-porous low-k dielectric technology called Black Diamond 3 last month at Semicon West. What really caught my ear though was the marketing claim that 1/3 of total chip power consumption (really energy) is in the interconnect. I thought about this a bit, and certainly for some designs this seemed to easily be quite po... » read more

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