Manufacturing Bits: May 27

Chip printing process; next-gen interconnect materials; carbon connections.


Chip printing process
Fraunhofer Institute for Manufacturing Technology and Advanced Materials has developed a novel way to make systems using electronic components, such as resistors, transistors and capacitors. Researchers use simple printers and a robot-assisted production line.

The components and other devices made from the technology could be used in various applications, such as digital thermometers, flexible solar cells and packages with built-in sensors.

Cylinder featuring functional surfaces acting as sensors. (Source: Fraunhofer IFAM)

Cylinder featuring functional surfaces acting as sensors.
(Source: Fraunhofer IFAM)

The robot-assisted production line can be integrated with modules for silk-screen, inkjet, dispenser, and aerosol-jet printing. Each printing technology can be used for different applications. For example, aerosol-jet printing enables the development of 10 micrometer components.

A multitude of substrates or functional inks can also be used. For example, the inks used by researchers include metals, ceramics, electrically conductive polymers and biomaterials. The substrates used in the process can be glass, textiles, metals, ceramic plates and others.

In the production flow, control software is used to program the desired product and printing method. Then, a robot picks up a substrate and places it on the first printing station. One example of a substrate is a circuit board.

If the task requires integrating 200-micrometer-wide circuit paths in the substrate, the component is sent to the dispenser. Basically, the dispenser is a piezoelectric dosing system. A material is applied to the component.

“If the conductor is to be connected to a sensor, the circuit board is then routed to the aerosol-jet printer,” according to Fraunhofer. “This high-resolution device prints the sensors. The circuit board then passes through other printers, depending on the application, before finally undergoing heat treatment in the furnace, in order to obtain the desired performance characteristics. The system is capable of printing on substrates up to the size of a DIN A3 sheet of paper, and can process components with a height of several centimeters.”

“The production line with its central robotic unit, component feeders, printing systems and heat treatment furnaces enables us to functionalize surfaces on a near-industrial scale,” said Volker Zöllmer, head of the Functional Structures department at Fraunhofer, on the organization’s Web site.

“The new production line enables us to process a wide range of different materials and combine them in many different ways to meet the customer’s requirements. This includes designing components capable of providing entirely new functions – such as window panes with integrated sensors for measuring temperature,” Zöllmer said. “Printed sensors can also be used to monitor building components, providing early warning of crack formation and other structural damage. They could also be useful in the car industry, where strain gages printed on aluminum surfaces by means of aerosol-jet printing could provide an early indication of material fatigue in body components.”

Next-gen interconnect materials
A big concern for chipmakers is the backend-of-the-line (BEOL). The BEOL is where the interconnects are formed within a device. Interconnects, those tiny wiring schemes in devices, are becoming more compact at each node, causing a resistance-capacitance (RC) delay in chips.

RC delay has been the topic of concern for years, but the problems won’t go away. In fact, they’re getting worse at the 20nm node and beyond.

In the interconnect flow, there are three main parts—metallization; low-k dielectrics; and the capping layer. In the metallization step, a structure undergoes a diffusion barrier etch step. Then, a via dielectric is deposited. An etch step then forms a gap, where the lines and vias are formed.

Then, a thin barrier layer of tantalum (Ta) and tantalum nitride (TaN) materials is deposited using physical vapor deposition (PVD). Ta is used to form the liner and TaN is for the barrier in a structure. The barrier layer is coated over by a copper seed barrier via PVD. And finally, the structure is electroplated with copper.

In many respects, this process has reached its limits, according to Tokyo Electron Ltd. (TEL). At the recent IEEE Joint Conference of the International Interconnect Technology Conference (IITC), TEL described a new metallization scheme for sub-10nm processing. It consists of ALD-based TaN barriers, a CVD-enabled ruthenium (Ru) liner, and a PVD-based copper dry-fill.

The depositions were performed on TEL’s cluster tool. For the barrier, PVD-based TaN has run out of steam, according to TEL. Atomic layer deposition (ALD) is a possible replacement for PVD, but ALD-enabled barriers have not delivered on their promises, according to TEL.

In TEL’s cluster tool, ALD-based TaN barriers were deposited at 350 degrees C. ALD barrier nucleation experiments were done on a blanket ultra low-k (k=2.5) substrate.

TEL showed results for TaN and TaAlN alloy films. Both ALD processes initialize well on ULK, but the better linearity of the TaAlN process indicated a superior surface initialization and film closure, according to TEL.

On the tool, CVD-based Ru was demonstrated as a replacement for PVD Ta liner/PVD copper seed due to its adhesion to copper, conformality and thickness control. It enabled copper wet-ability and fill, as well as up to 20% lower line resistance due to larger grain size, according to TEL.

Carbon connections
At IITC, Sharif University of Technology in Iran described a multilevel interconnect network of a macrocell for the 7.5nm node. The technology also makes use of carbon-based interconnects (CBIs).

In the future, CBI is a candidate to replace copper. CBI has demonstrated high thermal conductivity and current carrying capability. In fact, using a CBI, researchers from the Sharif University of Technology demonstrated the power dissipation associated with wires could be decreased by 32%.

Based on n-tier and developed n-tier methodologies, researchers devised a multilevel interconnect architecture of a 7.5nm ASIC macrocell. In the structure, researchers also implemented various CBIs, such as a zigzag single-layer graphene nanoribbon (GNR) and a single-wall carbon nanotube (SWCNT). Copper was also used in the experiment.

Researchers looked at three cases. In the first case, the interconnect was designed with copper only. In the second and third cases, the interconnect architecture was designed using copper and different CBIs.

In these two cases, the first (lowest) metal pair was designed with copper, the second with a 5-layer GNR and the others with SWCNT bundles. The only difference between the second case and the third case is that in the former, aspect ratio of SWCNT bundles is 2.1, while in the latter, it is equal to 0.5.

The technologies were compared from the view point of dynamic power dissipation, distribution of dynamic power dissipation in pairs, and total number of required metal pairs.

“It was shown that using CBI decreases power dissipation and (the) number of required metal pairs by 32% and 11% respectively,” according to researchers. “SWCNT bundles with smaller wire pitches (in comparison with Cu and GNR) satisfy delay constrain and decrease the number of required metal pairs. GNR interconnects decrease the number of wires per pair and power dissipation. Using GNR interconnects in non-local pairs, leads to excess of number of metal layers of 14. To use GNR interconnects in more than one pair, reverse wire pitch idea was proposed. Using SWCNT bundle and GNR interconnects in multilevel interconnect architecture of macrocells brings both advantages of low power dissipation.”