Memory Evolution Drives Requirements For Design Technology Co-Optimization


By Ricardo Borges and Anand Thiruvengadam As new technology nodes have become available, memory has been one of the most aggressive semiconductor applications to adopt advanced process technology. The relentless demand by users of electronic devices for more memory has ensured that investments in new nodes and processes would be quickly repaid by massive sales volumes. As each new node came ... » read more

Implementing Memory Encryption To Protect Data In Use


In my blog “The Methods of Memory Encryption to Protect Data in Use,” I discussed how the XTS/XEX mode of encryption was the appropriate choice for protecting data stored in and accessed from memory, also known as, protecting data in use. As a quick recap, XTS/XEX uses two keys, one key for block encryption, and another key to process a “tweak.” The tweak ensures every block of memory i... » read more

DDR5: How Faster Memory Speeds Shape The Future


Faster data processing requires faster memory. Double data rate synchronous dynamic random-access memory (DDR SDRAM) enables the world’s computers to work with the data in memory. DDR is used everywhere — not just in servers, workstations, and desktops, but it is also embedded in consumer electronics, automobiles, and other system designs. DDR SRAM is used for running applications and d... » read more

DRAM Thermal Issues Reach Crisis Point


Within the DRAM world, thermal issues are at a crisis point. At 14nm and below, and in the most advanced packaging schemes, an entirely new metric may be needed to address the multiplier effect of how thermal density increasingly turns minor issues into major problems. A few overheated transistors may not greatly affect reliability, but the heat generated from a few billion transistors does.... » read more

The Methods Of Memory Encryption To Protect Data In Use


In my blog “The Importance of Memory Encryption for Protecting Data in Use,” I discussed the growing industry consensus on the imperative of incorporating memory encryption in computing architectures. In part two of this series, I’ll explore the cipher algorithms and modes that can be used to protect data stored in and accessed from memory, or in other words, used to protect data in use. ... » read more

The Changing Mask Landscape


Semiconductor photomasks have undergone some major technology changes in the past few years after relatively minor changes for many years. New technologies such as multi-beam mask writers and extreme ultraviolet (EUV) lithography are major breakthroughs as they ramp into high-volume manufacturing. A new trend related to these technologies is the use of curvilinear features on photomasks. Aki... » read more

Every Walk’s A Hit: Making Page Walks Single-Access Cache Hits


As memory capacity has outstripped TLB coverage, large data applications suffer from frequent page table walks. We investigate two complementary techniques for addressing this cost: reducing the number of accesses required and reducing the latency of each access. The first approach is accomplished by opportunistically "flattening" the page table: merging two levels of traditional 4 KB p... » read more

Rambus To Buy Hardent


Rambus inked a deal to buy Hardent, an engineering services company, in order to accelerate Rambus' push into the CXL arena. Compute Express Link (CXL), developed primarily by Intel before being turned into an open industry standard, allows memory to be disaggregated within a data center and shared across multiple servers. This, in turn, lets data centers control how critical resources are a... » read more

The Importance Of Memory Encryption For Protecting Data In Use


Nowadays, as SoC (System-on-a-Chip) systems become more and more complex, security functions must grow accordingly to protect the semiconductor devices themselves and the sensitive information residing on or passing through them. While a Root of Trust security solution built into the SoCs can protect the chip and data resident therein (data at rest), many other threats exist which target interc... » read more

Interop Shift Left: Using Pre-Silicon Simulation for Emerging Standards


By Martin James, Gary Dick, and Arif Khan, Cadence with Suhas Pai and Brian Rea, Intel The Compute Express Link™ (CXL™) 2.0 specification, released in 2020, accompanies the latest PCI Express (PCIe) 5.0 specification to provide a path to high-bandwidth, cache-coherent, low-latency transport for many high-bandwidth applications such as artificial intelligence, machine learning, ... » read more

← Older posts Newer posts →