The Methods Of Memory Encryption To Protect Data In Use

By Rocky Zhang - 06 Jun, 2022 - Comments: 0

In my blog “The Importance of Memory Encryption for Protecting Data in Use,” I discussed the growing industry consensus on the imperative of incorporating memory encryption in computing architectures. In part two of this series, I’ll explore the cipher algorithms and modes that can be used to protect data stored in and accessed from memory, or in other words, used to protect data in use. ... » read more

The Changing Mask Landscape

By Jan Willis - 19 May, 2022 - Comments: 0

Semiconductor photomasks have undergone some major technology changes in the past few years after relatively minor changes for many years. New technologies such as multi-beam mask writers and extreme ultraviolet (EUV) lithography are major breakthroughs as they ramp into high-volume manufacturing. A new trend related to these technologies is the use of curvilinear features on photomasks. Aki... » read more

Every Walk’s A Hit: Making Page Walks Single-Access Cache Hits

By Arm - 11 May, 2022 - Comments: 0

As memory capacity has outstripped TLB coverage, large data applications suffer from frequent page table walks. We investigate two complementary techniques for addressing this cost: reducing the number of accesses required and reducing the latency of each access. The first approach is accomplished by opportunistically "flattening" the page table: merging two levels of traditional 4 KB p... » read more

Rambus To Buy Hardent

By Ed Sperling - 05 May, 2022 - Comments: 0

Rambus inked a deal to buy Hardent, an engineering services company, in order to accelerate Rambus' push into the CXL arena. Compute Express Link (CXL), developed primarily by Intel before being turned into an open industry standard, allows memory to be disaggregated within a data center and shared across multiple servers. This, in turn, lets data centers control how critical resources are a... » read more

The Importance Of Memory Encryption For Protecting Data In Use

By Rocky Zhang - 05 May, 2022 - Comments: 0

Nowadays, as SoC (System-on-a-Chip) systems become more and more complex, security functions must grow accordingly to protect the semiconductor devices themselves and the sensitive information residing on or passing through them. While a Root of Trust security solution built into the SoCs can protect the chip and data resident therein (data at rest), many other threats exist which target interc... » read more

Interop Shift Left: Using Pre-Silicon Simulation for Emerging Standards

By Cadence - 13 Apr, 2022 - Comments: 0

By Martin James, Gary Dick, and Arif Khan, Cadence with Suhas Pai and Brian Rea, Intel The Compute Express Link™ (CXL™) 2.0 specification, released in 2020, accompanies the latest PCI Express (PCIe) 5.0 specification to provide a path to high-bandwidth, cache-coherent, low-latency transport for many high-bandwidth applications such as artificial intelligence, machine learning, ... » read more

Choosing The Right Server Interface Architectures For High Performance Computing

By Jerry Lotto - 12 Apr, 2022 - Comments: 0

The largest bulk and cost of a modern high-performance computing (HPC) installation involves the acquisition or provisioning of many identical systems, interconnected by one or more networks, typically Ethernet and/or InfiniBand. Most HPC experts know that there are many choices between different server manufacturers and the options of form factor, CPU, RAM configuration, out of band management... » read more

Automate Memory Test Through A Shared Bus Interface

By Harshitha Kodali - 12 Apr, 2022 - Comments: 0

The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point for testing the memories. A shared bus architecture allows testing and repairing memories within IP cores through a single access point referred to as a shared bus interface. Within this interface... » read more

Data Retention Performance Of 0.13-μm F-RAM Memory

By Infineon - 06 Apr, 2022 - Comments: 0

F-RAM (Ferroelectric random access memory) is a non-volatile memory that uses a ferroelectric capacitor for storing data. It offers higher write speeds over flash/EEPROM. This white paper provides a brief overview of data retention performance of F-RAM memory. Click here to read more. » read more

CXL and OMI: Competing or Complementary?

By Bryon Moyer - 23 Mar, 2022 - Comments: 1

System designers are looking at any ideas they can find to increase memory bandwidth and capacity, focusing on everything from improvements in memory to new types of memory. But higher-level architectural changes can help to fulfill both needs, even as memory types are abstracted away from CPUs. Two new protocols are helping to make this possible, CXL and OMI. But there is a looming question... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.