Carbon Nanotube DRAM

By Susan Rambo - 23 Aug, 2018 - Comments: 0

An IP design house has developed a scalable DRAM replacement using carbon nanotubes (CNTs) that abolishes the DRAM refresh rate, stores the content permanently, has better timing than DRAM and is scalable. And it lasts for somewhere between 300 and 12,000 years. “Carbon nanotube memory—it sounds so sexy that I could just shut up and not say anything,” said Bill Gervasi, principal syste... » read more

Architects Firmly In Control

By Ed Sperling - 23 Aug, 2018 - Comments: 0

Moore's Law isn't dead, but it certainly isn't what it used to be. While there may be three or four more generations of node shrinks ahead, the power/performance benefits of scaling are falling off. This is evident in new chip architectures that were introduced at this year's Hot Chips conference. Originally started to show off the latest CPUs and co-processors, in past years the focus has b... » read more

The New Deep Learning Memory Architectures You Should Know About

By eSilicon - 22 Aug, 2018 - Comments: 0

Artificial intelligence (AI) has come a long way. While our parents grew up with the dream to one day roam with robots, today we are interviewing Sophia, a citizen of Saudi Arabia, who is also the first humanoid robot to be granted a citizenship in any country. Deep learning, a brain-inspired discipline of AI has been around for a long time but has only recently taken off due to abundant data, ... » read more

AI Architectures Must Change

By Brian Bailey - 13 Aug, 2018 - Comments: 4

Using existing architectures for solving machine learning and artificial intelligence problems is becoming impractical. The total energy consumed by AI is rising significantly, and CPUs and GPUs increasingly are looking like the wrong tools for the job. Several roundtables have concluded the best opportunity for significant change happens when there is no legacy IP. Most designs have evolved... » read more

High-Performance Memory At Low Cost Per Bit

By Liji Gopalakrishnan - 09 Aug, 2018 - Comments: 0

Hardware developers of deep learning neural networks (DNN) have a universal complaint – they need more and more memory capacity with high performance, low cost and low power. As artificial intelligence (AI) techniques gain wider adoption, their complexity and training requirements also increase. Large and complex DNN models do not fit on the small on-chip SRAM caches near the processor. This ... » read more

Impact Of IP On AI SoCs

By Ron Lowman - 09 Aug, 2018 - Comments: 2

The combination of mathematics and processing capability has set in motion a new generation of technology advancements with an entire new world of possibilities related to Artificial Intelligence. AI mimics human behavior using deep learning algorithms. Neural networks are what we define as deep learning, which is a subset of machine learning, which is yet a subset of AI, as shown in Figure 1. ... » read more

Pros, Cons Of ML-Specific Chips

By Ed Sperling - 27 Jul, 2018 - Comments: 1

Semiconductor Engineering sat down with Rob Aitken, an Arm fellow; Raik Brinkmann, CEO of OneSpin Solutions; Patrick Soheili, vice president of business and corporate development at eSilicon; and Chris Rowen, CEO of Babblelabs. What follows are excerpts of that conversation. To view part one, click here. Part two is here. SE: Is the industry's knowledge of machine learning keeping up with th... » read more

Leti’s Next Focus

By Mark LaPedus - 19 Jul, 2018 - Comments: 0

Emmanuel Sabonnadière, chief executive of Leti, sat down with Semiconductor Engineering to discuss R&D trends, a new deal with Soitec, and the latest developments at the France-based research organization. Leti is a research institute of CEA Tech. What follows are excerpts of that conversation. SE: Leti recently formed an alliance with Soitec. Under the terms, Leti and Soitec are formin... » read more

Embedded FPGA Design Considerations

By Ed Sperling - 09 Jul, 2018 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about interconnects, memory, different design approaches, and why foundry processes are critical to eFPGA design. https://youtu.be/FngrgDnJn9c » read more

Defining Edge Memory Requirements

By Ann Mutschler - 20 Jun, 2018 - Comments: 0

Defining edge computing memory requirements is a growing problem for chipmakers vying for a piece of this market, because it varies by platform, by application, and even by use case. Edge computing plays a role in artificial intelligence, automotive, IoT, data centers, as well as wearables, and each has significantly different memory requirements. So it's important to have memory requirement... » read more

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tag: memory

Carbon Nanotube DRAM

Architects Firmly In Control

The New Deep Learning Memory Architectures You Should Know About

AI Architectures Must Change

High-Performance Memory At Low Cost Per Bit

Impact Of IP On AI SoCs

Pros, Cons Of ML-Specific Chips

Leti’s Next Focus

Embedded FPGA Design Considerations

Defining Edge Memory Requirements

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