tag: memory

Performance-IP: Less Memory Latency
By Ed Sperling - 02 May, 2017 - Comments: 0

The combination of more functionality on chips plus more contention for memories is forcing companies to look at different ways to improve performance. Just adding more processing power doesn't guarantee improved performance, and throwing more memory at a problem—either SRAM or multiple levels of cache—is expensive and not always faster. There are too many processors and too many request... » read more

Inside Lithography And Masks
By Mark LaPedus - 01 May, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" comment="IMEC"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; David Fried, chief technology officer at [getentity id="22210" e_name="Cov... » read more

Why Is TCAM Essential For The Cloud?
By eSilicon - 27 Apr, 2017 - Comments: 0

With port speeds exceeding 100Gbps, route lookups that are fundamental to all routers have relied on ternary content addressable memories (TCAMs) to provide a lookup response within a clock cycle. However, TCAMs in discrete form are expensive, consume a lot of power, compete for precious real estate on the printed circuit board (PCB), and often lack required flexibility. Embedding a TCAM block ... » read more

Enabling Magnetic Tunnel Junctions Array Processing For Embedded STT MRAM
By Mahendra Pakala - 24 Apr, 2017 - Comments: 0

The semiconductor industry is entering a new era of next-generation memory technologies, with several major inflections taking shape. Among these is the emergence of Magnetic RAM (MRAM). Over several posts, I’ll provide background on what is driving the adoption of MRAM, highlight some of the initial challenges and discuss progress on making STT MRAM commerically viable. Today, a typical m... » read more

The Week In Review: Design
By Jesse Allen - 21 Apr, 2017 - Comments: 0

Tools Mentor unveiled new formal-based technologies in the Questa Verification Solution. It offers formal-based RTL-to-RTL equivalence checking flows optimized for verification of manual low-power clock gating, bug fix and ECO validation, and ISO 26262 safety mechanism verification, which the company says which can reduce verification turnaround time by 10X. The app also offers expanded cloc... » read more

Time For Massively Parallel Testing
By Jeff Dorsch - 12 Apr, 2017 - Comments: 0

Time is money in electronics, as in other industries, and the more time that is invested in testing chips means more costs being added to the product in question. To speed up testing for memory devices and other semiconductors, test equipment vendors have resorted to parallel testing technology, simultaneously testing multiple chips at a time. The industry also is turning to system-level tes... » read more

Intelligent Compute Engines Driving Today’s Automobiles Need Better Security
By Paolo Piacentini - 06 Apr, 2017 - Comments: 0

Driving a modern car or truck today is like driving a complex computer system which has the capability to transport people and freight from a geographic point to another through the road infrastructure and, to do so, it just happens it has an engine and wheels. With automotive systems moving towards consolidation of workloads, there is a need and benefit of having faster networking throughpu... » read more

The Week In Review: Design
By Jesse Allen - 31 Mar, 2017 - Comments: 0

M&A Siemens closed the acquisition of Mentor Graphics, making Mentor now part of Siemens' product lifecycle management (PLM) software business. The $4.5 billion deal, announced last November, brings Siemens into the IC design tool and embedded software markets and expands Siemens' multi-physics and electronic simulation capabilities in the growing digital twin space, which ties together ... » read more

HBM Upstages DDR In Bandwidth, Power
By Ann Mutschler - 30 Mar, 2017 - Comments: 1

For graphics, networking, and high performance computing, the latest iteration of high-bandwidth memory (HBM) continues to rise up as a viable contender against conventional DDR, GDDR designs, and other advanced memory architectures such as the Hybrid Memory Cube. [getkc id="276" kc_name="HBM"] enables lower power consumption per I/O and higher bandwidth memory access with a more condensed f... » read more

Optimal Memory Strategies: Where HBM2 Fits
By eSilicon - 23 Mar, 2017 - Comments: 0

How are you going to build your next big product? Whether it’s in the networking, wireless, mobile or computing market, you are now increasing the functionality of your product. It needs to be able to do many tasks – fast, at low power, and pack as much functionality into the tiniest area for cost effectiveness. What does this mean for the embedded memory content? It is growing rapidly. ... » read more

← Older posts Newer posts →

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy