Inside Lithography And Masks

Experts at the table, part 3: EUV, DSA, nanoimprint, nanopatterning, and best guesses for how far lithography can be extended.


Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at IMEC; Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries; David Fried, chief technology officer at Coventor; Naoya Hayashi, research fellow at Dai Nippon Printing (DNP); and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To view part one, click here. Part two is here.

SE: For some time, Canon has been developing and shipping nanoimprint lithography systems. (Nanoimprint lithography resembles a hot embossing process. Tiny structures are patterned onto a template or mold using an e-beam tool, and then the patterns are pressed into a resist on a substrate, enabling tiny features.) Nanoimprint is still targeted for NAND, right?

Hayashi: For 2xnm, like 24nm and 26nm line and space, nanoimprint could reach production last year. Then, last year as Toshiba said, we confirmed that certain yields of 15nm 2D NAND were made using nanoimprint. But then, that represents the last products for 2D NAND.

SE: At 16nm or 15nm, NAND flash vendors are moving from traditional 2D or planar NAND to . Is nanoimprint being used for 3D NAND?

Hayashi: Some are confirming the yield of 3D NAND.

SE: DNP has been making the templates for nanoimprint lithography. What’s the status?

Hayashi: The nanoimprint template is 1:1. We are currently making the templates for 3D NAND. The most critical layers are the holes. As we discussed before, for any type of lithography like optical and EUV, the shot noise is a big issue for making the contact holes. With nanoimprint, we can get a very narrow gap for contact holes with good CD uniformity and pattern fidelity. That’s a good place to use nanoimprint.

SE: What are some of the remaining challenges with nanoimprint?

Hayashi: There are still some defectivity issues. We still need another two digits of improvement to extend the technology for another memory like DRAM. For logic, it’s still far away. Overlay is currently like the 3nm range. It’s enough for NAND. The DRAM people want to shrink that number.

Fig. 1: Nanoimprint schematic. Source: DNP

SE: Let’s move to directed self-assembly (DSA). (DSA is a technology that makes use of block copolymer materials. In the DSA process, the copolymers undergo a separation phase. Then, when used in conjunction with a pre-pattern that directs the orientation of the materials, the copolymers self-assemble into a tiny pattern. DSA was a rising star in the next-generation lithography (NGL) landscape, but the technology has lost momentum and has been pushed out.) Where are we in DSA?

McIntyre: It’s not a secret that the momentum has slowed down a little for DSA compared to what it was a few years ago. But it hasn’t gone away. It’s not completely off the table. There are applications where we think it’s potentially still feasible. For example, Imec has been working on DSA quite a while. We focus on three activities in DSA. One is called Chips Flow. It’s a chemo-epitaxy flow for creating hexagonal arrays of holes, which is potentially interesting for the DRAM folks. We have just recently decreased the defectivity compared to where it was six months ago or so. If we can keep going on that path, it may be a viable option for the DRAM folks. There is another DSA application. It’s not going to beat out SAQP for forming dense lines and spaces at the 20nm-something pitch. But if we go below 20nm, and have to do something like SAOP, DSA could be a potential alternative there, as well. For this, there is a lot of focus on high-chi materials, leading to really dense pitches. Then, the third application could potentially go hand-in-hand with EUV, essentially as a healing technique to smooth the roughness that you get in EUV holes. The template-based approach is a nice way to do that. So, DSA has slowed down a little bit, but it’s not off the table.

Fried: My suspicion is that if we see DSA, it will not be in a pattern multiplication mode. It will be in a pattern healing mode. And the likelihood of seeing something in a pattern healing mode actually seems reasonable. There are defectivity concerns, of course. But not having to lump pattern multiplication on top of the defectivity concerns in pattern healing seems like a slightly relaxed set of criteria, and that could be a reality.

McIntyre: Pattern healing is getting there. It’s a potentially interesting technique that could be used in our toolbox.

Fig. 2: DSA flow. Source: University of Chicago Institute of Molecular Engineering

SE: Let’s talk about another futuristic patterning technology called selective deposition or ALD nanopatterning. (Using atomic layer deposition (ALD) tools, selective deposition involves a process of depositing materials and films in exact places.) Where is selective deposition now?

McIntyre: It is definitely very interesting. There is a potential for various uses such as growing dielectrics on dielectrics, or dielectrics on metals. What we are trying to understand are the fundamentals of which materials can you grow on what other materials. You often see a different behavior between blanket wafers. You get nice growth, but if you try to grow the material in actual patterns, the behavior can be completely different. So the next step will be to put it in a couple of applications and see where it could potentially help you.

Levinson: It is nice to know there are some innovative concepts out there. But it does take a long time for something like this to go from a laboratory into manufacturing. We have to wait and see. There are many techniques that fail at some point for some reason or another. We’ll have to see which ones pan out and which ones don’t.

McIntyre: Right now, this technology is sort of in the research sandbox type stage. It might see some applications in some of these self-aligned techniques like a fully self-aligned via. For a while, we’ve done self-aligned vias in one direction. But if you want to line it up the other direction as well, it requires some topography to take advantage of it. There are a couple of ways to do that topography. You can do it with either traditional metal etching or use something like selective deposition to grow little pieces of metals. Then, you use them to help self-align a via landing on a metal line or something like that.

SE: Let’s make some predictions. What will happen in the future, say in the next 5 years or more, from your vantage point or area of interest?

Fujimura: I have faith that this community of people and a $300 billion semiconductor industry are going to figure out a way to solve the problems. From a need point of view, we have a computational design platform. We know GPU acceleration. So we use supercomputers and build them ourselves. I can tell you we need computing power. IoT and PCs don’t need to be incredibly faster. But you need more computational power for AI, deep learning and all of these hot topics. Today, just doing simulation, we need computing power. We can do a lot better if we had more. So, I don’t see an end of that demand. We could figure a way to utilize 100 times more computing power if we had it.

Fried: When I was in graduate school, I won a fellowship and met with (co-founder and former Intel CEO) Andy Grove. It was a long time ago. It was the quarter-micron time or even earlier. People asked Andy Grove about why do we need a faster computer. He had a list of applications that we just didn’t have the compute power for at that time. He brought up one that always stuck in the back of my head—voice recognition. Grove said, ‘Voice recognition is terrible right now.’ Now, if you look at it, voice recognition is still awful. So you have AI and machine learning and the need for voice recognition. There are drivers that would want that extra compute power. There will be demand for this. Whether we make a cost-effective answer to that demand is going to determine whether there is a 5nm or 3nm node. We can build it. It’s going to be demand and the cost-efficiency of a solution to that demand.

Levinson: I have a great deal of confidence in the patterning community to continue our ability to scale geometrically for some time. What’s unclear are the devices and the transistors. It’s also unclear about the interconnect technology, whether that’s going to be able to continue to scale. But there are definitely ways to extend the technology other than scaling.

McIntyre: I do believe we will be able to continue to make things smaller. The device folks will figure it out. Maybe the front-end device stuff won’t scale as much as it has in the past. But there does seem to be room to grow or shrink in the backend with new metals and direct-metal etch techniques. There seems to be enough things that are plausible out there. So, we are probably going to keep scaling, maybe not at the same rate that we did a number of years ago. Physical scaling might continue to slow down. In addition, we will probably see high NA EUV. It will be used first for an EPE reduction scheme. If you can go to higher NA, you go to higher image contrast. You get less stochastics in your materials.

Fried: We’ve milked drift-diffusion field-effect devices for five generations longer than anyone said we could. We may break that at some point. But then, there are tunnel devices and then you can go to very low voltage devices. There are all these things that may eventually kick in when we really break with what we have now. There are a huge pile of these things. So if you can pattern it, we can make something.

Related Stories
Ready For Nanoimprint?
NGL option gains ground and adherents for single-digit process nodes, but more work is still needed.
What Happened To DSA?
Alternative patterning technology makes incremental gains, but the big money is still behind EUV.
Inside Advanced Patterning
What’s in store for chipmakers at 7nm, 5nm and beyond, and why atomic-level etch and deposition are getting new attention.
Uncertainty Grows For 5nm, 3nm
Nanosheets and nanowire FETs under development, but costs are skyrocketing. New packaging options could provide an alternative.


memister says:

Actually, for DSA there has been some work done on via pairs:, including by IMEC, Globalfoundries, others. Two for the price of one can halve the number of masks (e.g., 4 down to 2).

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