tag: memory

DDR5 Memory Enables Next-Generation Computing
By John Eble - 13 Apr, 2023 - Comments: 0

Computing main memory transitions may only happen once a decade, but when they do, it is a very exciting time in the industry. When JEDEC announced the publication of the JESD79-5 DDR5 SDRAM standard in 2021, it signaled the beginning of the transition to DDR5 server and client dual-inline memory modules (Server RDIMMs, Client UDIMMs and SODIMMs). We are now firmly on this path of enabling the ... » read more

How To Safeguard Memory Interfaces By Design
By Dana Neustadter - 06 Apr, 2023 - Comments: 0

By Dana Neustadter and Brett Murdock In 2017, the credit bureau Equifax announced that hackers had breached its system, unleashing the personal information of 147-million people. As a result, the company has settled a class action suit for $425 million to aid those impacted, including identity theft, fraud, financial losses, and the expenses to clean up the damage. Whether the threat is iden... » read more

Impact Of Increased IC Performance On Memory
By Ed Sperling - 30 Mar, 2023 - Comments: 0

Increasing performance in advanced semiconductors is becoming more difficult as chips become more complex. There are more physical effects to contend with, different use cases, and challenges in making memory go faster. In addition, aging effects that once were ignored are now becoming critical concerns. Steven Woo, fellow and distinguished inventor at Rambus, talks about different factors that... » read more

Feasibility of Using Domain Wall-Magnetic Tunnel Junction for Magnetic Analog Addressable Memories
By Technical Paper Link - 23 Mar, 2023 - Comments: 0

A new technical paper titled "Domain Wall-Magnetic Tunnel Junction Analog Content Addressable Memory Using Current and Projected Data" was published by researchers at UT Austin and Samsung Advanced Institute of Technology (SAIT). Abstract "With the rise in in-memory computing architectures to reduce the compute-memory bottleneck, a new bottleneck is present between analog and digital conver... » read more

A Comparative Evaluation Of DRAM Bit-Line Spacer Integration Schemes
By Dempsey Deng - 16 Mar, 2023 - Comments: 0

With decreasing dynamic random-access memory (DRAM) cell sizes, DRAM process development has become increasingly difficult. Bit-line (BL) sensing margins and refresh times have become problematic as cell sizes have decreased, due to an increase in BL parasitic capacitance (Cb). The main factor impacting Cb is the parasitic capacitance between the BL and the node contact (CBL-NC) [1]. To reduce ... » read more

How Low Can You Go? Pushing The Limits Of Transistors
By Synopsys - 08 Mar, 2023 - Comments: 0

Deep low voltage enablement of embedded memories and logic libraries to achieve extreme low power: Rising demand for cutting-edge mobile, IoT, and wearable devices, along with high compute demands for AI and 5G/6G communications, has driven the need for lower power systems-on-chip (SoCs). This is not only a concern for a device’s power consumption when active (dynamic power), but also when... » read more

How To Build Resilience Into Chips
By Ed Sperling and Ann Mutschler - 27 Feb, 2023 - Comments: 0

Disaggregating chips into specialized processors, memories, and architectures is becoming necessary for continued improvements in performance and power, but it's also contributing to unusual and often unpredictable errors in hardware that are extremely difficult to find. The sources of those errors can include anything from timing errors in a particular sequence, to gaps in bonds between chi... » read more

Dealing With Performance Bottlenecks In SoCs
By Brian Bailey - 23 Feb, 2023 - Comments: 0

A surge in the amount of data that SoCs need to process is bogging down performance, and while the processors themselves can handle that influx, memory and communication bandwidth are straining. The question now is what can be done about it. The gap between memory and CPU bandwidth — the so-called memory wall — is well documented and definitely not a new problem. But it has not gone away... » read more

Process Innovations Enabling Next-Gen SoCs and Memories
By Laura Peters - 20 Feb, 2023 - Comments: 0

Achieving improvements in performance in advanced SoCs and packages — those used in mobile applications, data centers, and AI — will require complex and potentially costly changes in architectures, materials, and core manufacturing processes. Among the options under consideration are new compute architectures, different materials, including thinner barrier layers and those with higher th... » read more

Devices And Transistors For The Next 75 Years
By Laura Peters - 16 Feb, 2023 - Comments: 0

The 75th anniversary of the invention of the transistor sparked a lively panel discussion at IEDM, spurring debate about the future of CMOS, the role of III-V and 2D materials in future transistors, and what will be the next great memory architecture.[1] Industry veterans from the memory, logic, and research communities see high-NA EUV production, NAND flash with 1,000 layers, and hybrid bon... » read more

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