tag: Mentor Graphics

EDA, IP Sales Up
By Ed Sperling - 30 Jun, 2016 - Comments: 0

EDA and IP revenue increased 4.5% in Q1, a significant increase given the semiconductor industry was flat last year and that EDA sales dropped 1.9% in Q4 of 2015. Total sales were $1.962 billion, up from $1.877 in Q1 of 2015. The big surprise, though, was Japan, which grew 12%. Japan's semiconductor business has been in a deep slump for several years. "It's been a long time since we've se... » read more

Uncertainty Rocks Chip Market
By Ed Sperling - 30 Jun, 2016 - Comments: 1

The semiconductor industry is undergoing sweeping changes in every direction, making it far more difficult to figure out which path to take next, when to take it, and how to get there. The next few years will redefine which semiconductor companies emerge as leaders, which ones get pushed down or out or absorbed into other companies, and which markets will be the most lucrative. And that coul... » read more

Electrical-Mechanical Tool Flow Revisited
By Ann Mutschler - 30 Jun, 2016 - Comments: 0

For many years, the design tool industry has entertained the idea of combining both electrical and mechanical design into a single user experience, with a single database as a foundation. Major tool vendors, at least on the electrical side, have taken the matter seriously and confirm that activities towards a single flow have been considered, particularly as the [getkc id="7" kc_name="EDA"] ... » read more

Improve DFT Verification And Meet Time-To-Market Goals With Emulation
By Steve Dondershine - 30 Jun, 2016 - Comments: 0

What if all the DFT verification on your next big chip could be completed before tape-out? This “shift-left” of DFT verification would eliminate the need for shortcuts in verification and allow for more types of verification. The benefits of faster and earlier DFT verification include higher confidence in the “golden” RTL, eliminating DFT from the critical path of tape-out, and more pre... » read more

Can Verification Meet In The Middle?
By Brian Bailey - 30 Jun, 2016 - Comments: 0

Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

Reducing Design Risk With Testbench Acceleration
By Mentor, a Siemens Business - 29 Jun, 2016 - Comments: 0

Part 1 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three papers, architectural and modeling requirements are described, followed by a recommended systematic approach for maximizing overall testbench acceleration speed-up and achieving your ultimate performan... » read more

Blog Review: June 29
By Jesse Allen - 29 Jun, 2016 - Comments: 0

Ansys' Justin Nescott checks out the world's first electric highway for trucking in this week's top five tech picks. Plus, some cool houses, Boston Dynamics' giraffe-bot, and a drum kit in a backpack. Applied's Matt Cogorno takes a look at the challenges facing etch methods as devices keep getting smaller. Synopsys' Apoorva Mathur digs into the energy efficient aspects of the MIPI M-PHY a... » read more

The Week In Review: Design
By Jesse Allen - 24 Jun, 2016 - Comments: 0

Tools & IP Synopsys uncorked PHY and Controller IP for PCI Express 4.0 architecture, which the company says reduces latency by up to 20% and area by 15% compared to the previous implementation. The IP supports lane margining to assess performance variation tolerance. PLDA announced a PCIe 4.0 development platform, and provides a PCIe 3.0-x8 (upstream) to PCIe 4.0-x4 (downstream) Integ... » read more

Pattern Matching In Test And Yield Analysis
By Geir Eide - 23 Jun, 2016 - Comments: 1

By Jonathan Muirhead and Geir Eide It’s no secret that a successful yield ramp directly impacts integrated circuit (IC) product cost and time-to-market. Tools and techniques that help companies ramp to volume faster, while also reducing process and design variability, can be the difference between profit and loss in a competitive market. And while pattern matching technology has been aroun... » read more

Advanced Packaging Options, Issues
By Ed Sperling - 23 Jun, 2016 - Comments: 0

Systems in package are heading for the mass market in applications that demand better performance and lower power. As they do, new options for cutting costs are being developed to broaden the appeal of this approach as an alternative to shrinking features. Cost has been one of the big deterrents for widespread adoption of [getkc id="82" kc_name="2.5D"]. Initially, the almost universal compla... » read more

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