tag: Mentor Graphics

Blog Review: July 29
By Jesse Allen - 29 Jul, 2015 - Comments: 0

NASA estimates they could reduce the cost of colonizing the moon to $10 billion, with mining fuel from the lunar surface potentially making the satellite a gas station on the way to Mars or beyond. This week's top five articles from Ansys' Bill Vandermark are mostly out of this world, but there's a down-to-earth aspect as airless tires roll closer to inclusion in consumer vehicles. How will ... » read more

What Will 7nm And 5nm Look Like?
By Mark LaPedus - 23 Jul, 2015 - Comments: 0

Citing an assortment of undisclosed manufacturing issues, Intel in July pushed out the introduction of its 10nm chip and process technology to the second half of 2017. This is roughly six or more months later than expected. With the delay at 10nm, [getentity id="22846" e_name="Intel"] also pushed out its process cadence from 2 to 2.5 years. Other foundries, meanwhile, are struggling to keep ... » read more

Ensuring Optimal Performance For Physical Verification
By Mentor, a Siemens Business - 22 Jul, 2015 - Comments: 0

By accessing the most recently qualified version of foundry rule files, users get the most efficient rule implementations. By adopting the most recent version of Calibre, users get the latest improvements in available operations, operation performance, data hierarchy optimization and total scaling, providing the best possible performance and minimizing runtimes. Design teams running full-chip D... » read more

Blog Review: July 22
By Jesse Allen - 22 Jul, 2015 - Comments: 0

It's been a hot summer for high-level synthesis, says Cadence's Dave Pursley in a collection of the season's HLS highlights spanning DAC to SystemC Japan. Mentor's Harry Foster continues his survey of functional verification with a look at the adoption trends of various verification technologies, and the reasons one-third of projects use emulation or FPGA prototyping. Synopsys' Navraj Nan... » read more

How Much Security Is Enough?
By Ed Sperling - 20 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss the current state of [getkc id="223" kc_name="security"] and what must be done in the future, with Denis Noël, head of cyber security solutions at [getentity id="22499" e_name="NXP"]; Serge Leef, vice president of new ventures at [getentity id="22017" e_name="Mentor Graphics"]; Andreas Kuehlman, senior vice president and general manager of the soft... » read more

Blog Review: July 15
By Jesse Allen - 15 Jul, 2015 - Comments: 0

From 7nm to steel that's stronger than steel, there have been a wave of breakthrough announcements this week. Ansys' Bill Vandermark rounds them up in his top five engineering articles. In his latest installments of the 2014 Functional Verification Study, Mentor's Harry Foster focuses on the growing complexity of ASIC/IC designs and the changes in resource use that resulted. In a new vide... » read more

Power Breaks Everything
By Ed Sperling - 15 Jul, 2015 - Comments: 2

The emphasis on lowering power in everything from wearable electronics to data centers is turning into a perfect storm for the semiconductor ecosystem. Existing methodologies need to be fixed, techniques need to be improved, and expectations need to be adjusted. And even then the problems won't go away. In the past, most issues involving power—notably current leakage, physical effects such... » read more

Moore Memory Problems
By Brian Bailey - 09 Jul, 2015 - Comments: 0

The six-transistor static memory cell (SRAM) has been the mainstay of on-chip memory for several decades and has stood the test of time. Today, many advanced SoCs have 50% of the chip area covered with these memories and so they are critical to continued scaling. “The SRAM being used in modern systems is similar to the SRAM they were using in the 1970s and 1980s,” says Duncan Bremner, ch... » read more

Divide And Conquer: A Power Verification Methodology Approach
By Ann Mutschler - 09 Jul, 2015 - Comments: 0

It’s no secret that the power verification challenge has grown by leaps and bounds in the recent past, especially considering design complexity and the sharp rise in the number of power domains in an SoC. As a result, SoC teams want to apply a rigorous [getkc id="10" kc_name="Verification"] flow, observed Gabriel Chidolue, verification technologist at [getentity id="22017" e_name="Mentor G... » read more

Cloud 2.0
By Ed Sperling - 09 Jul, 2015 - Comments: 0

Corporate data centers are reluctant adopters of new technology. There is too much at stake to make quick changes, which accounts for a number of failed semiconductor startups over the past decade with better ideas for more efficient processors, not to mention rapid consolidation in other areas. But as the amount of data increases, and the cost of processing that data decreases at a slower rate... » read more

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