More Multiply-Accumulate Operations Everywhere


Geoff Tate, CEO of Flex Logix, sat down with Semiconductor Engineering to talk about how to build programmable edge inferencing chips, embedded FPGAs, where the markets are developing for both, and how the picture will change over the next few years. SE: What do you have to think about when you're designing a programmable inferencing chip? Tate: With a traditional FPGA architecture you ha... » read more

From Constraints to Tape-Out: Towards A Continuous AMS Design Flow


The effort in designing analog/mixed-signal (AMS) integrated circuits is characterized by the largely manual work involved in the design of analog cells and their integration into the overall circuit. This inequality in effort between analog and digital cells increases with the use of modern, more complex technology nodes. To mitigate this problem, this paper presents four methods to improve ex... » read more

Improving Simulation Throughput Using The Xcelium Parallel Logic Simulator


Simulators have been around for a long time. First, there were interpreters in the ‘80s and ‘90s, and despite being relatively slow, they were a big step up from fabricating the design and hoping it worked. However, as designs continued to increase in size, the interpreters could not keep up with simulation needs, and innovation was required for simulators to keep pace with new technology. ... » read more

From Constraints To Tape-Out: Towards A Continuous AMS Design Flow


The effort in designing analog/mixed-signal (AMS) integrated circuits is characterized by the largely manual work involved in the design of analog cells and their integration into the overall circuit. This inequality in effort between analog and digital cells increases with the use of modern, more complex technology nodes. To mitigate this problem, this paper presents four methods to improve ex... » read more

Using Analog For AI


If the only tool you have is a hammer, everything looks like a nail. But development of artificial intelligence (AI) applications and the compute platforms for them may be overlooking an alternative technology—analog. The semiconductor industry has a firm understanding of digital electronics and has been very successful making it scale. It is predictable, has good yield, and while every de... » read more

ON Semiconductor Conquers Verification Challenges


Motor controller IC design for automotive applications, such as power mirror, seats, door locks, and door lift control, creates exceptional verification challenges. Particularly because these ICs must work for over 10 years and they live in harsh environments including -40° C to 150° C temperature ranges, voltages ranging from 7V to 40V, and potential electrostatic discharge and electromagnet... » read more

Boosting Analog Reliability


Aveek Sarkar, vice president of Synopsys’ Custom Compiler Group, talks about challenges with complex design rules, rigid design methodologies, and the gap between pre-layout and post-layout simulation at finFET nodes. https://youtu.be/JRYlYJ31LLw » read more

Mixed-Signal Methodology Guide


ClioSoft wrote the chapter on SoC design data management in Cadence’s "Mixed-Signal Methodology Guide." Register to receive an electronic copy of this chapter. Introduction Software teams have long used version control and data management systems and they have become an integral part of a software development environment. Practically, no significant software project is started without a so... » read more

Cracking The Mixed-Signal Verification Code


Rapid digitization in IoT, automotive, industrial, and communication industry segments are fueling semiconductor industry growth. This growth follows the “More than Moore” paradigm, where new design starts are spread across mature to advanced manufacturing nodes based on end-application targets. With this digitalization, data has become the most valuable resource. Mixed-signal designs pl... » read more

Simplifying Mixed-Signal Verification With The Symphony Platform


As complexity of mixed-signal SoCs grows, verification engineers cannot rely on the “divide and conquer” approach of verifying digital and analog blocks individually and then stitching them together for full-chip verification. Verification teams need to run an increasing number of mixed-signal simulations at the top level as well as at the subsystem to make sure there are no functional erro... » read more

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