tag: Moore’s Law

More Than Moore At iMAPS
By Paul McLellan - 02 Dec, 2021 - Comments: 0

San Diego recently hosted the 54th International Symposium on Microelectronics. That's a very generic title, so you should know that it is run by iMAPS, the International Microelectronics Assembly and Packaging Society. Generally, the conference is just known as iMAPS. One of the keynotes was given by Cadence's KT Moore (in person). His presentation was titled "More Moore or More than Moore: a... » read more

What’s Next For Transistors And Chiplets
By Mark LaPedus - 21 Oct, 2021 - Comments: 5

Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

Data Tsunami Pushes Boundaries Of IC Interconnects
By Ann Mutschler - 22 Sep, 2021 - Comments: 0

Rapid increases in machine-generated data are fueling demand for higher-performance multi-core computing, forcing design teams to rethink the movement of data on-chip, off-chip, and between chips in a package. In the past, this was largely handled by the on-chip interconnects, which often were a secondary consideration in the design. But with the rising volumes of data in markets ranging fro... » read more

Inside Intel’s Ambitious Roadmap
By Mark LaPedus and Ed Sperling - 23 Aug, 2021 - Comments: 2

Ann Kelleher, senior vice president and general manager of Technology Development at Intel, sat down with Semiconductor Engineering to talk about the company’s new logic roadmap, as well as lithography, packaging, and process technology. What follows are excerpts of that discussion. SE: Intel recently disclosed its new logic roadmap. Beyond Intel 3, the company is working on Intel 20A. Wit... » read more

Designing Chips In A ‘Lawless’ Industry
By Ed Sperling - 02 Aug, 2021 - Comments: 2

The guideposts for designing chips are disappearing or becoming less relevant. While engineers today have many more options for customizing a design, they have little direction about what works best for specific applications or what the return on investment will be for those efforts. For chip architects, this is proving to be an embarrassment of riches. However, that design freedom comes wit... » read more

CEO Outlook: Chiplets, Longer IC Lifetimes, More End Markets
By Ed Sperling - 14 Jul, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, longer IC lifetimes, and a spike in the number of end applications with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; an... » read more

An Introduction To Domain-Specific Accelerators
By Roddy Urquhart - 24 Jun, 2021 - Comments: 0

After 50 years, Moore’s Law, Dennard Scaling, and Amdahl’s Law are failing. The semiconductor industry much change, and processor paradigms must change with it. So what exactly are domain-specific accelerators and why are they so important in light of the failure of these semiconductor scaling laws? » read more

The Road To Domain-Specific Accelerators
By Roddy Urquhart - 27 May, 2021 - Comments: 0

For about fifty years, IC designers have been relying on different types of semiconductor scaling to achieve gains in performance. Best known is Moore’s Law, which predicted that the number of transistors in a given silicon area and clock frequency would double every two years. This was combined with Dennard scaling, which predicted that with silicon geometries and supply voltages shrinki... » read more

Steep Spike For Chip Complexity And Unknowns
By Ed Sperling - 05 May, 2021 - Comments: 0

Cramming more and different kinds of processors and memories onto a die or into a package is causing the number of unknowns and the complexity of those designs to skyrocket. There are good reasons for combining all of these different devices into an SoC or advanced package. They increase functionality and can offer big improvements in performance and power that are no longer available just b... » read more

Foundry Wars Begin
By Mark LaPedus - 19 Apr, 2021 - Comments: 3

Leading-edge foundry vendors are gearing up for a new, high-stakes spending and technology race, setting the stage for a possible shakeup across the semiconductor manufacturing landscape. In March, Intel re-entered the foundry business, positioning itself against Samsung and TSMC at the leading edge, and against a multitude of foundries working at older nodes. Intel announced plans to build ... » read more

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