CEO Outlook: Chiplets, Longer IC Lifetimes, More End Markets

How the end of scaling and the electrification of everything are changing chip design.


Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, longer IC lifetimes, and a spike in the number of end applications with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What follows are excerpts of a panel discussion held by the SEMI ESD Alliance. Part one of this discussion can be found here.

SE: Intel and AMD are focusing on chiplets. How do you see this unfolding for the rest of the industry?

Segars: A lot of our partners are very interested in chiplets to deal with rising complexity and as a way to build ever-more-efficient systems. Ideally, you want to integrate everything onto one die, but you can’t always do that. So you integrate chiplets in a package to put these much more sophisticated modules together. It is possible to do this, but it’s still pretty hard today. It’s black-belt chip design that requires very close interaction with who’s doing the design, who’s doing the manufacturing and who’s doing the packaging. This will become a technology that’s used by lots of people. And there’s a huge role for the EDA industry to play here in helping abstract some of the difficulty away from the physical issues that we deal with to make it a much more commonplace technology for people to use. That will open up another dimension of design. Everyone talks about the slowing down of Moore’s Law. You can’t just make transistors smaller and smaller. The close integration of these die is one of the ways we’re going to see architectures and designs evolving into the future to deliver more and more performance. There’s a role around standardization to make it easy to mix and match these chiplets. There’s also a lot of work ahead to create the interconnects between these chiplets. Over the next 5 to 10 years these are issues that are going to get resolved, and it will become a common design technique.

Taheri: Integrating these chiplets into any kind of advanced packaging becomes a real challenge. There is a lot of work going on involving interconnecting these die, and there is work around Intel’s Embedded Multi-Die Interconnect Bridge (EMIB), which is supposed to solve the connection of heterogeneous chiplets in terms of architecture and bandwidth requirements. That requires a lot of 2D and 3D simulations. For EDA companies, there is a lot of work to be done to come up with standards that are agreeable to the industry.

SE: How do these get tested? These are no longer standard designs.

Kibarian: We’ve been looking at standardization of the equipment in the assembly flow because that’s still very much a human-intensive activity. It’s becoming more lights-out for things like data collection on that equipment, because you need to understand what happened. But for sophisticated chip-in-package, you need chip ID — the ability to understand where it came from, meaning what factory, which wafer, and which part of that wafer. With a lot of components in those package, like passives or a microphone or infrared sensor, there is no traceability. Having traceability through that flow is very important, and it’s becoming a requirement. When you get to final test, you need to know what that chip looks like at wafer sort. We have one customer where that’s an absolute requirement. Testing is becoming a process where you need to be able to pass information from each stage up and down. You know what’s happening at wafer sort and final test, and transmitting of data is now a requirement for these technologies. Right now this is a bespoke solution for each product. When the infrared sensor came out for the iPhone, it was a bespoke assembly flow. The package also was bespoke. Now we need to add a lot of computerization so that when you do a design, you hopefully can get to a more mix-and-match scenario. Today this is much more engineering-intensive.

SE: On top of that, these chips are supposed to last longer. So in addition to all the other issues we’ve been dealing with, there is now a silicon lifecycle management challenge. What changes from a design standpoint?

Sawicki: When we first started looking at this, we questioned whether this was an evolution of data or a revolution. We finally concluded it was an evolutionary revolution. Years ago, we started testing a chip for manufacturability. Then, over the past decade or so, we began adding in data so you could make decisions that affected things like functional safety applications. So auto manufacturers may run built-in self-tests every 10 to 20 seconds to make sure the chip is still operating, and you port that into the system software. That has evolved into things like structural integrity monitoring, and now we’re monitoring for performance, reliability, intrusion — all aspects of things that aren’t actually function, but which ensure the functioning over time. Sometime within the next four to five years we’ll see chips in data centers reporting on their own health, reporting on the overall environment, to enable people to better manage these data centers. When you have the vast amount of data is running on the cloud with the person managing the hardware not knowing where the software is, then you need a lot more autonomy in terms of how the hardware is performing. That trend is going to hit fast, and it’s going to be very impactful in terms of how the silicon goes through its overall lifecycle.

SE: When you develop IP you don’t know how it’s going to be used or what it’s going to be near in order to properly characterize it. How does that affect the development of the IP?

Tan: IP can be mission-critical, which affects production and the lifecycle. So it needs to be silicon-proven. But you also need to know how much of a buffer you can create in terms of the temperature and the voltage or any other fluctuation that can cause a data center or an automobile to fail. You can over-provision it, and you can monitor it over time. Some of this data is mission-critical, and you need it for these devices to operate properly.

SE: In the past, we had lots of guideposts for the industry, such as Moore’s Law and the ITRS roadmap. How has that affected design?

Drako: I wouldn’t actually characterize those as guideposts. They were methods to predict. Competition drives everyone to go as fast as they can, and that still continues. We’ve reached limitations for how small we can make things. But we have come up with other ways to put more into a design by stacking chips on top of each other or putting them into modules. The ingenuity of engineers kicks in to make chips better and faster. We’ve reached the point where parallelism, driven by GPUs and AI applications, has created the need for even more parallelism. So rather than smaller, faster and stronger, we’re going a lot wider, which is creating the need for more data. It’s the next step of where we’re going. It’s a slightly different direction, but it’s all enhancements.

Kibarian: This is certainly interesting for engineers. But right now it’s also interesting to the investment community and to the general public. The President of the United States talks about it because of the shortage. We should use this opportunity to communicate what’s in front of us, because what Moore’s Law did was tell the world we’re always going to do something more exciting and better. We haven’t communicated what cadence we’re following today. There’s great work out there. [Jonathan] Koomey did great work around performance per dollar per watt. And we, as an industry, need to do a better job communicating where we are going over the next 10 to 20 years. It’s really valuable.

Drako: I agree there’s value in that. We’re pushing up against the limits of physics, even though we continue make headway.

Segars: One of the things that makes it more challenging, and certainly more interesting, is the industry is no longer going in just one direction. It isn’t about whether we can make smaller and smaller transistors. We’ve got a simultaneous explosion in edge AI, tiny sensors that need leverage one set of technologies. We’ve got massive compute that’s going on in the cloud where you need to worry about the efficiency of that. We’ve got new network technologies evolving that require new wireless and RF technologies. It’s going in multiple directions at once, which makes it difficult to use guideposts. It’s very interesting, and we should use that to get people really interested in this industry and to join it. That’s ultimately what we need.

Drako: There are three major kinds of pull. There is the low-power, portable phone type of devices. There is the data center, with more compute. And there is the AI pull, which is massive training and learning. All three of those require different architectures in the CPU, in manufacturing, and in the execution and the engineering. We haven’t had that many strong pulls in the past.

Segars: Another one is the electrification of everything. Power electronics is becoming an area that is really interesting because we have to rewire the entire world. We have to hook up different sources of energy and power things differently with technology most people haven’t been looking at for a really long time.

Taheri: Another dimension is software-defined anything. There are so many application areas that. It’s very difficult to have one standard to work on all of this stuff. It’s also very exciting.

SE: Given the electrification of everything, what does EDA look like in the future?

Taheri: The electrification of homes, buildings, roads, and everything else is a mega-trend. Each of us has to contribute to that based on our expertise.

Drako: EDA will continue as it has for 50 years. The EDA industry is about to hit its stride in yet a new phase of value with the application of learning systems and AI, helping engineers to do designs more efficiently and effectively. There also is EDA slowly moving to the cloud. We’re in this hybrid phase now. The cloud can be very expensive for compute, because Amazon and Microsoft have their margins, and there is a massive investment in data centers. So there is a huge migration of wanting to use the cloud for some things, on demand, and still using your own data centers for others. There will be an AI impact in the tools for routing, design, analysis, layout, synthesis, and everything we do. One might argue that Synopsys 25 years ago created the first AI product. The next phase, with neural nets, will make designers even more productive.


Reedman says:

The biggest forward-movement in power electronics is electric vehicles. Silicon Carbide provides enough of a benefit that the cost hit is acceptable even in the sell-your-mother-to-save-a-nickel automobile market. The LED lighting market is now mature (thanks to progress in Gallium Nitride). The silicon drivers for all these power pieces are worth real money to the semiconductor manufacturers who land the business.

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