tag: SRAM

Performance Increasingly Tied To I/O
By Ed Sperling - 18 Jan, 2017 - Comments: 0

Speeding up input and output is becoming a cornerstone for improving performance and lowering power in SoCs and ASICs, particularly as scaling processors and adding more cores produce diminishing returns. While processors of all types continue to improve, the rate of improvement is slowing at each new node. Obtaining the expected 30% to 50% boost in performance and lower power no longer can ... » read more

Using Automated Pattern Matching For SRAM Physical Verification
By Elven Huang - 15 Dec, 2016 - Comments: 0

How often have you struggled to verify static random-access memory (SRAM) blocks in your design? And how often, no matter how much time you spend on them, do they end up causing manufacturing issues? Memory is a critical component in today’s SoC designs, often consuming 50% or more of the die area. SRAM blocks are typically assembled in a layout using a set of specific intellectual propert... » read more

SRAM Physical Verification With Calibre Pattern Matching
By Mentor, a Siemens Business - 14 Dec, 2016 - Comments: 0

Traditional SRAM verification flows can require significant resources to implement and support, and still miss critical errors that result in manufacturing defects. Using the Calibre Pattern Matching automated pattern-based solution provides accurate results, avoids costly mask re-spins, and is easily updated to add newly developed SRAM IP cells. To read more, click here. » read more

Executive Insight: Charlie Cheng
By Ed Sperling - 03 Nov, 2016 - Comments: 0

[getperson id="11073" comment="Charlie Cheng"], CEO of [getentity id="22135" e_name="Kilopass Technology"], sat down with Semiconductor Engineering to talk about the limitations of DRAM, how to get around them, and who's likely to do that. What follows are excerpts of that discussion. SE: What are the top market segments from a [getkc id="22" kc_name="memory"] standpoint? Cheng: The top o... » read more

Moore’s Law Debate Continues
By Ann Mutschler - 02 Nov, 2016 - Comments: 0

Does shrinking devices still make sense from a cost and performance perspective? The answer isn’t so simple anymore. Still, the discussion as to whether semiconductors are still on track with [getkc id="74" comment="Moore's Law"] occurs on a frequent enough basis to continue analyzing at least some of the dynamics at play. There is much speculation about what happens after 7nm, as well as ... » read more

Tech Talk: Embedded Memories
By Ed Sperling - 25 Oct, 2016 - Comments: 0

Dave Eggleston, vice president of embedded memory at GlobalFoundries, talks about the pros and cons of new types of embedded memory, including which work best for certain applications and with various advanced packaging options. [youtube vid=7D9zoA9FFIw] » read more

Sorting Out Next-Gen Memory
By Mark LaPedus - 22 Sep, 2016 - Comments: 8

In the data center and related environments, high-end systems are struggling to keep pace with the growing demands in data processing. There are several bottlenecks in these systems, but one segment that continues to receive an inordinate amount of attention, if not part of the blame, is the memory and storage hierarchy. [getkc id="92" kc_name="SRAM"], the first tier of this hierarchy, is... » read more

May The Cheapest Memory Win
By Ed Sperling - 11 Aug, 2016 - Comments: 4

There are a number of new memory types on the horizon. So why are we still using DRAM, SRAM and hard disk drives developed decades ago? The answer is complicated. Memory, whether it’s on-chip static RAM cache or off-chip dynamic RAM—or flash storage or spinning magnetic media—is really a stack of data storage technologies that need to work seamlessly together and with other non-memory ... » read more

The Future Of Memory
By Ed Sperling - 16 Jun, 2016 - Comments: 2

Semiconductor Engineering sat down to discuss future memory with Frank Ferro, senior director of product management for memory and interface IP at [getentity id="22671" e_name="Rambus"]; Marc Greenberg, director of product marketing at [getentity id="22035" e_name="Synopsys"]; and Lisa Minwell, [getentity id="22242" e_name="eSilicon"]'s senior director of [getkc id="43" kc_name="IP"] marketing.... » read more

How Many Cores? (Part 2)
By Ed Sperling - 21 Mar, 2016 - Comments: 1

New chip architectures and new packaging options—including fan-outs and 2.5D—are changing basic design considerations for how many cores are needed, what they are used for, and how to solve some increasingly troublesome bottlenecks. As reported in part one, just adding more cores doesn't necessarily improve performance, and adding the wrong size or kinds of cores wastes power. That has s... » read more

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