A New Memory Contender?

FeFETs are a promising next-gen memory based on well-understood materials.


Momentum is building for a new class of ferroelectric memories that could alter the next-generation memory landscape.

Generally, ferroelectrics are associated with a memory type called ferroelectric RAMs (FRAMs). Rolled out by several vendors in the late 1990s, FRAMs are low-power, nonvolatile devices, but they are also limited to niche applications and unable to scale beyond 130nm.

While FRAMs continue to ship, the industry has also been developing a different memory type called a ferroelectric FET (FeFET). Instead of using traditional FRAM materials, FeFETs and related technologies harness the ferroelectric properties in hafnium oxide, sometimes referred to as ferroelectric hafnium oxide. (FeFETs are different than a logic transistor type called finFETs).

Still in the R&D stage, a FeFET isn’t a new device, per se. For FeFETs, the idea is to take an existing logic transistor with a high-k/metal-gate stack based on hafnium oxide, and then to modify the gate insulator with ferroelectric properties. The resulting structure is the same transistor with a scalable, embedded FeFET memory with low-power and nonvolatile properties. In theory, that should outperform today’s embedded flash memories.

Fig. 1: How to make a FeFET. Source: Ferroelectric Memory Co.

Others are working on different types of FeFET-based, nonvolatile devices. It sounds like a simple concept, but there are several challenges, such as integration issues, data retention, reliability and cost. “(FeFETs are) promising, but it’s still early,” said Greg Wong, an analyst with Forward Insights.

There are other challenges as well. “For a new emerging memory technology, the toughest part is to get credibility and confidence on the customer side that your solution is real,” said Stefan Müller, chief executive of Ferroelectric Memory Co. (FMC), a startup that is developing FeFETs.

Still, FeFETs and related technologies are gaining steam. Here are the most recent developments in the arena:

• GlobalFoundries, FMC, NaMLab, Fraunhofer and others have reached a major milestone by demonstrating an embedded, nonvolatile FeFET in a 22nm FD-SOI process. The technology is slated for qualification in 2019, although there is no timetable for production.
• Imec is developing a scheme that would replace current DRAM materials with ferroelectric hafnium oxide, creating a new class of nonvolatile DRAM-like memories. In addition, Imec is also developing a stacked ferroelectric device that resembles a 3D NAND.
• SK Hynix, LAM Research, Versum and others recently presented a paper on the switching mechanisms of such devices, of which the group calls a 1T-FeRAM and a 3D FeNAND.
• A growing number of groups are exploring ferroelectric hafnium oxide for a next-generation logic transistor type, commonly referred to as a negative-capacitance field-effect transistor (NC-FET). NC-FETs are a potential transistor candidate for 3nm and beyond.

3D FeNAND, ferroelectric DRAMs and NC-FETs are still in the early stages of R&D, and it’s too soon to say if these technologies will ever make it into production. The big proving ground is the FeFET being developed by GlobalFoundries, FMC and others.

If it flies, the FeFET joins a crowded field in the next-generation memory market. Other new memory types, such as 3D XPoint, , ReRAM and even traditional FRAM, are shipping. Potentially, FeFETs will compete with some but not all of these technologies.

Next-gen memory race
For years, the industry has been developing the next-generation memory types and for good reason—the traditional memories have an assortment of limitations.

For example, DRAM, which is used as the main memory in systems, is fast and cheap. But DRAM is volatile. It loses data when the power is turned off in a system.

NAND and NOR flash memory are also cheap. Flash is nonvolatile and stores the data even when the power is off. In operation, though, flash undergoes several read/write cycles, which is a slow process.

This is where the new memories fit. Generally, the next-generation memory types are fast, nonvolatile and provide unlimited endurance. They also provide bit-alterable, erase-free functions, making them potentially ideal replacements for DRAM and flash. But these new memories also rely on exotic materials and complicated switching mechanisms, so they have taken longer to develop. At the same time, the industry continues to scale DRAM and flash, making it difficult for the new memory types to get a foothold in the market.

Still, the industry is beginning to ramp up some of the new memory types. Here is a simple explanation of the landscape:

Intel and Micron are ramping up 3D XPoint, a next-generation technology based on phase-change memory. 3D XPoint is a standalone device, which is used to speed up the operations in a solid-state drive (SSD).
• Everspin and others are developing a next-generation MRAM technology called spin-transfer torque magnetoresistive RAM (STT-MRAM). Used for embedded or standalone applications, STT-MRAM uses the magnetism of electron spin to provide nonvolatile properties in chips.
• Several vendors and foundries are developing resistive RAM (ReRAM) for standalone and embedded apps. In ReRAM, a voltage is applied to a material stack, creating a change in the resistance that records data in the memory.
• Cypress, Fujitsu, Panasonic, TI and others are shipping microcontrollers (MCUs) with embedded FRAM.

Fig. 2: Spin torque MRAM technology. Source: Everspin

Fig. 3: ReRAM in action. Source: Adesto

FRAMs are widely misunderstood, as ferroelectric materials are not ferromagnetic. “[Ferroelectric memory] writes an application using an electric field only and no current flow,” FMC’s Müller explained. “All of the other emerging memory concepts, like resistive RAM, phase-change memory, and MRAM all write by driving a current through the memory cell.”

The FRAM is based on a(one transistor, one capacitor (1T-1C) storage cell design. Using a ferroelectric capacitor to store data, FRAM is a low-power, nonvolatile memory with unlimited endurance, making it ideal for various embedded chip applications.

Typically, FRAMs consist of a thin ferroelectric film, based on lead zirconate titanate (PZT). “The atoms in the PZT change polarity in an electric field, thereby producing a power efficient binary switch,” according to Cypress.

Fig. 4: Traditional FRAM. Source: Cypress

FRAMs have some issues, however. “The classical FRAM is exotic from the materials point of view,” Müller said. “FRAM has not scaled beyond the 130nm technology node due to the fact that only planar capacitors can be used and the traditional ferroelectric films are not scalable. This has prevented traditional FRAM from widespread adoption.”

With FeFET, which is different than traditional FRAM, proponents hope to solve these issues. Several years ago the industry stumbled upon a new discovery, namely the ferroelectricity properties in hafnium oxide. Researchers discovered a crystal phase can be stabilized in the process of doping hafnium oxide. “Within that crystal phase, the oxygen atoms of hafnium oxide can reside in two stable positions, shifting either up or down according to the polarity of an externally applied electric field,” according to FMC.

Hafnium oxide is a well-understood material. For some time, chipmakers have used hafnium oxide as the gate stack material for high-k/metal-gate structures in logic devices at 28nm and beyond. For FeFETs, the idea is to leverage properties of ferroelectric hafnium oxide rather than to create a new device architecture using exotic materials.

In FMC’s technology, for example, the ideal is to take an existing transistor. Then, using a deposition process, a silicon-doped hafnium oxide material is deposited into the gate stack of the transistor, creating a ferroelectric property. FMC’s scheme also eliminates the need for a capacitor, enabling a one transistor memory cell or a 1T-FeFET technology.

“In FeFETs, a permanent dipole is formed within the gate dielectric itself, splitting the threshold voltage of the ferroelectric transistor into two stable states,” Müller said. “Accordingly, binary states can be stored in the FeFETs similar to how it is done in a flash memory cell.”

Fig. 5: FeFET (n-type functionalty). When the ferroelectric polarization points downward (left), electrons invert the channel region, permanently bringing the FeFET into the “on” state. If polarization points up (middle), permanent accumulation is created and the FeFET is in the “off” state. Source: FMC.

In theory, the technology is compelling. “You have hafnium oxide in every cutting-edge transistor. It’s the gate dielectric,” he said. “If you do it cleverly and modify the hafnium oxide, you can actually transition your logic transistor, which loses a state when you remove the power, into a nonvolatile transistor. It remains in state when the power is removed.”

FeFETs are still in R&D and not ready for prime time. But if it does work, customers would have yet another choice in the next-generation memory world. 3D XPoint, FRAM, MRAM, ReRAM and others are also in the arena.

So which new memory technology will prevail? That’s not entirely clear, because no one memory can handle all requirements. Each new memory type has its place. And the new memory types are taking some sockets away from traditional memories. But by and large, traditional DRAM and NAND continue to dominate the memory hierarchy.

Fig. 6: Memory hierarchy Source: Imec

Embedded memory wars

In the memory space, the emerging battle is taking place in the embedded market. Today’s MCUs integrate several components on the same chip, such as a CPU, SRAM and embedded memory. The CPU executes the instructions. SRAM is integrated on the chip to store data.

Embedded memory, such as EEPROM and NOR flash, are used for code storage and other functions. “With EEPROM, each bit is two transistors. And each byte can be erased or re-programmed,” said Jim Handy, an analyst with Objective Analysis, in a recent interview. “On each block (with NOR flash), we have one huge transistor that does the erase for all of the bits on the block. A huge transistor still saves a lot of chip space, compared to two transistors per bit.”

Embedded flash (eFlash) is robust, making it ideal for industrial applications. For example, automotive OEMs have stringent requirements and NOR fits the bill. “Performance-driven automotive MCUs are a driving force behind eFlash,” said Walter Ng, vice president of U.S. sales at UMC.

NOR has some limitations, as the write speeds are slow. NOR is also becoming more expensive as it moves from 40nm to 28nm. And it’s unclear if NOR can scale beyond 28nm.

Suppliers of next-generation memories hope to fill the void. “Emerging RAMs seemingly provide a possible solution,” Ng said. “Yet, it remains to be seen how such technologies will be received by the automotive community.”

Regardless, the embedded memory market is heating up. Several foundries—such as GlobalFoundries, Samsung, TSMC and UMC—are developing embedded STT-MRAM. In addition, SMIC, TSMC and UMC are developing embedded ReRAM.

FeFET is the new kid on the block. In 2009, Fraunhofer, GlobalFoundries and NaMLab began to explore FeFETs. Later, FMC was spun out of NaMLab.

In 2014, the group demonstrated a simple FeFET array based on a 28nm CMOS process. Then, at the recent IEDM conference, GlobalFoundries, Fraunhofer, NaMLab and FMC presented new results that brought FeFETs one step closer towards commercialization.

The group demonstrated an embedded FeFET in a 22nm FD-SOI process. “It’s a very low-cost approach for getting a very dense type of memory,” said Gary Patton, CTO at GlobalFoundries.

The FeFET, according to the IEDM paper, has a cell size as small as 0.025μm². The device consists of a 32MBit array with program/erase pulses in the 10ns range at 4.2 volts. It has a temperature retention rate up to 300 °C.

Initially, FeFETs are targeted for the embedded nonvolatile memory market for consumer applications. “It is around two orders of magnitude faster in write (than traditional eFlash). We write in the 10ns regime, where flash writes in the 1ms to 10ms regime,” FMC’s Müller said.

The technology is promising. “They are farther along than anyone else,” said Jan Van Houdt, a distinguished member of the technical staff at Imec. “They are going for the embedded case right away. It’s probably going to work.”

FeFETs face an uphill battle in embedded memory space for automotive, where the temperature requirements are more stringent. Automotive OEMs, though, are indeed looking at STT-MRAM, as the technology can withstand higher temperatures.

What’s next?
For its part, Imec is developing ferroelectric technology on two fronts. One involves a new type of a nonvolatile DRAM-like device, while the other is a standalone storage device that resembles 3D NAND.

DRAM is based on a 1T1C cell structure. In operation, the charge in the capacitor will leak or discharge when the transistor is turned off. So, the capacitor must be refreshed every 64 milliseconds, which, in turn, consumes power in a system.

Inside DRAM’s vertical capacitor structure, there is a metal-insulator-metal (MIM) material stack. In the MIM stack, a high-k material is sandwiched between two zirconium dioxide layers. This is sometimes called the ZAZ capacitor.

Imec and others are exploring the idea of replacing the zirconium dioxide material with ferroelectric hafnium oxide in the DRAM. Hafnium oxide in its ferroelectric state is similar to zirconium dioxide.

With the technology, Imec is developing a ferroelectric DRAM-like device with nonvolatile properties, which does not require a refresh operation.

There are challenges, of course. Scaling the vertical 1T1C capacitor is difficult for DRAM at each node. That won’t change for a ferroelectric DRAM-like device, as the device is also configured with a 1T1C cell.

Fig. 7: DRAM roadmap Source: Imec

Another possibility is that the industry could develop a one transistor (1T) DRAM-like device with nonvolatile properties. That is a capacitor-less ferroelectric DRAM-like device.
But even with ferroelectric hafnium, ferroelectric-based DRAMs face some challenges. “The problem is that it has some endurance limitations. DRAM almost has unlimited endurance. With ferroelectrics, that has to be proven,” Imec’s Van Houdt said.

Imec also is pursuing a ferroelectric device technology that resembles a 3D NAND. The technology, sometimes referred to as a 3D FeNAND, is built using a 3D NAND-based manufacturing flow.

“It’s low voltage and nonvolatile. Power consumption is much lower. It would be faster, because it’s a high-k material. So your transistor is going to drive much more current than NAND,” Van Houdt said.

The problem? “It’s sort of a NAND replacement. But, of course, to replace NAND is almost impossible,” he said.

So if it does fly, the device could fit somewhere in the storage-class memory hierarchy. But the technology is still five to ten years away from entering the commercial market.

There are other issues. For example, in a paper at IEDM, SK Hynix, Lam and others found that the actual switching speeds are slower than expected in ferroelectric hafnium oxide materials due to extrinsic disorders.

SK Hynix, Lam and others found a way to control the grain size of the silicon-doped hafnium oxide, which in turn boosts the speed of the material set. “We successfully demonstrated that Si:HfO2 consists of controlled nano-grains with a FE property of Ec ~0.5MV/cm, which is a half of the ordinary Si:HfO2, and the domain switching speed reaches ~3 times faster than that of ordinary grain sized Si:HfO2,” according to the paper.

What are NC-FETs?
There are other applications for ferroelectric hafnium oxide. For some time, UC Berkeley and others continue to pursue the NC-FET, a next-generation logic transistor targeted for 3nm or beyond.

Like the FeFET, the NC-FET isn’t a new device. In NC-FET, the gate stack in an existing transistor is modified with ferroelectric hafnium oxide. The film thicknesses are slightly different in an NC-FET as compared to a FeFET.

“That’s why there is so much keen interest,” said Mike Chudzik, senior director of the Transistor and Interconnect Group at Applied Materials. “It’s a simple swap of a dielectric for a ferroelectric. I would put it alongside tunnel FETs.”

NC-FETs are steep sub-threshold slope devices for low-power apps. It would compete more with a tunnel FET (TFET), a low-power transistor type aimed for 3nm and beyond.

“Essentially, a ferroelectric is like a voltage amplifier. You put one voltage on it. Because the way it interacts, it amplifies the voltage. That’s why you get this enhanced sub-threshold slope,” Chudzik said.

With the technology, UC Berkeley is exploring the idea of extending today’s finFET and FD-SOI technologies down to 2nm. UC Berkeley refers to its technologies as NC-finFET and NC-FD-SOI.

To be sure, the NC-FET is still in the early stages. “There is a lot of promise and interest in it, but there are a lot of unanswered questions,” Chudzik said.

In the short term, though, the FeFET is the first technology that could appear from the promising material set. This, in turn, could set off a wave of R&D in the arena. Or, like other technologies, it could simply fall by the wayside.

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Santosh Kurinec says:

Nice article. My group is working on FeFETs research as well.

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