tag: SRAM

MRAM Evolves In Multiple Directions
By Bryon Moyer - 11 Mar, 2021 - Comments: 1

Magnetoresistive RAM (MRAM) is one of several new non-volatile memory technologies targeting broad commercial availability, but designing MRAM into chips and systems isn't as simple as adding other types of memory. MRAM isn’t an all-things-for-all-applications technology. It needs to be tuned for its intended purpose. MRAMs targeting flash will not do as well targeting SRAMs, and vice vers... » read more

Hidden Costs In Faster, Low-Power AI Systems
By Ed Sperling - 20 Jan, 2021 - Comments: 1

Chipmakers are building orders of magnitude better performance and energy efficiency into smart devices, but to achieve those goals they also are making tradeoffs that will have far-reaching, long-lasting, and in some cases unknown impacts. Much of this activity is a direct result of pushing intelligence out to the edge, where it is needed to process, sort, and manage massive increases in da... » read more

Imec’s Plan For Continued Scaling
By Paul McLellan - 14 Jan, 2021 - Comments: 0

At IEDM in December, the opening keynote (technically "Plenary 1") was by Sri Samevadam of Imec. His presentation was titled "Towards Atomic Channels and Deconstructed Chips." He presented Imec's view of the future of semiconductors going forward, both Moore's Law (scaling) and More than Moore (advanced packaging and multiple die). It is always interesting to hear Imec's view of the world sinc... » read more

MPU Vs. MCU
By Bryon Moyer - 01 Dec, 2020 - Comments: 1

There was a time when microprocessors and microcontrollers were distinct devices. There was never a question as to which one you were dealing with. But changes in the memory architecture have muddied the distinction in modern devices. There are a number of ways in which microprocessors and microcontrollers could possibly be differentiated. But there is no universal agreement as to how that s... » read more

Dealing With Sub-Threshold Variation
By Bryon Moyer - 12 Nov, 2020 - Comments: 0

Chipmakers are pushing into sub-threshold operation in an effort to prolong battery life and reduce energy costs, adding a whole new set of challenges for design teams. While process and environmental variation long have been concerns for advanced silicon process nodes, most designs operate in the standard “super-threshold” regime. Sub-threshold designs, in contrast, have unique variatio... » read more

Slower Metal Bogs Down SoC Performance
By Bryon Moyer - 15 Oct, 2020 - Comments: 0

Metal interconnect delays are rising, offsetting some of the gains from faster transistors at each successive process node. Older architectures were born in a time when compute time was the limiter. But with interconnects increasingly viewed as the limiter on advanced nodes, there’s an opportunity to rethink how we build systems-on-chips (SoCs). ”Interconnect delay is a fundamental tr... » read more

DRAM, 3D NAND Face New Challenges
By Mark LaPedus - 21 Sep, 2020 - Comments: 1

It’s been a topsy-turvy period for the memory market, and it's not over. So far in 2020, demand has been slightly better than expected for the two main memory types — 3D NAND and DRAM. But now there is some uncertainty in the market amid a slowdown, inventory issues and an ongoing trade war. In addition, the 3D NAND market is moving toward a new technology generation, but some are enc... » read more

What Happened To Execute-in-Place?
By Bryon Moyer - 25 Aug, 2020 - Comments: 0

Executing code directly from non-volatile memory, where it is stored, greatly simplifies compute architectures — especially for simple embedded devices like microcontrollers (MCUs). However, the divergence of memory and logic processes has made that nearly impossible today. The term “execute-in-place,” or ”XIP,” originated with the embedded NOR memory in MCUs that made XIP viable. ... » read more

Memory Access In AI Systems
By Ed Sperling - 27 Jul, 2020 - Comments: 0

Memory access is a key consideration in AI system design. Ron Lowman, strategic marketing manager for IP at Synopsys, talks about how memory affects overall power consumption, why partitioning of on-chip and off-chip is so critical to performance and power, and how this changes from the cloud to the edge. » read more

Moving Data And Computing Closer Together
By Bryon Moyer - 09 Jul, 2020 - Comments: 2

The speed of processors has increased to the point where they often are no longer the performance bottleneck for many systems. It's now about data access. Moving data around costs both time and power, and developers are looking for ways to reduce the distances that data has to move. That means bringing data and memory nearer to each other. “Hard drives didn't have enough data flow to cr... » read more

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