tag: Synopsys

New Data Center Protocols Tackle AI
By Bryon Moyer - 17 Mar, 2025 - Comments: 0

Compute nodes in AI and HPC data centers increasingly need to reach out beyond the chip or package for additional resources to process growing workloads. They may commandeer other nodes in a rack (scale-up) or employ resources in other racks (scale-out). The problem is there currently is no open scale-up protocol. So far this task has been dominated by proprietary protocols, because much of ... » read more

Chip Industry Week In Review
By The SE Staff - 14 Mar, 2025 - Comments: 0

ASML and imec signed a five-year strategic partnership to advance semiconductor innovation and sustainable technology. The collaboration will leverage ASML’s full product portfolio, including high-NA EUV, DUV immersion, and advanced metrology tools, within imec’s pilot line for sub-2nm R&D. Supported by EU and national funding, it will also drive research in silicon photonics, memory, a... » read more

Easier Assertion Development And Debug With Simulation Replay
By Vin Liao - 13 Mar, 2025 - Comments: 0

By Vin Liao and Robert Ruiz Assertions and assertion IP (AIP) are a core part of the register transfer level (RTL) verification environment for all modern chip development projects. Assertions can be considered as statements of design intent, specifying how the design should behave—and not behave—under specified conditions. They range from simple statements, for example, that a multi-bit... » read more

Chiplets Add New Power Issues
By Ann Mutschler - 13 Mar, 2025 - Comments: 0

Delivering and managing power are becoming key challenges in the rollout of chiplets, adding significantly to design complexity and forcing chipmakers to weigh tradeoffs that can have a big impact on the performance, reliability, and the overall cost of semiconductors. Power is a concern for every chip and chiplet design, even if the specifics differ based on the application. Systems vendors... » read more

Integrating Data From Design, Manufacturing, And The Field
By Adam Kovac - 13 Mar, 2025 - Comments: 0

Chip design is starting to include more options to ensure chips behave reliably in the field, boosting the ability to tweak both hardware and software as chips age. The basic problem is that as dimensions become smaller, and as more features are added into devices — especially with heterogeneous assemblies of chiplets running some type of AI — the potential for thermally induced structur... » read more

LLE-Aware Design Methodology To Avoid Timing And Power Pessimism
By Synopsys - 12 Mar, 2025 - Comments: 0

As chips move to ever-finer geometries, the active region (diffusion) shapes of neighboring cells can impact timing analysis and power calculations for the entire design. The LLE (Local Layout Effect) impact must be measured, but the impact is reflected very conservatively using conventional approaches. This paper describes a LLE-aware design methodology that mitigates the conservatism of co... » read more

Blog Review: Mar. 12
By Jesse Allen - 12 Mar, 2025 - Comments: 0

Cadence's P. Saisrinivas explains the relationship between drive strength and cell delay and why it is key to choose the appropriate drive strength to meet timing constraints while minimizing power and area. Siemens' Daniel Berger and Dirk Hartmann tackle the readout problem of accurately measuring the state of a quantum system after it has undergone a quantum computation, which becomes incr... » read more

Speeding Down Memory Lane With Custom HBM
By Faisal Goriawalla - 11 Mar, 2025 - Comments: 0

With the goal of increasing system performance per watt, the semiconductor industry is always seeking innovative solutions that go beyond the usual approaches of increasing memory capacity and data rates. Over the last decade, the High Bandwidth Memory (HBM) protocol has proven to be a popular choice for data center and high-performance computing (HPC) applications. Even more benefit can be rea... » read more

Automation And AI Improve Failure Analysis
By Laura Peters - 11 Mar, 2025 - Comments: 0

When a chip malfunctions it’s the job of the failure analysis engineer to determine how it failed or significantly deviated from its key performance metrics. The cost of failure in the field can be huge in terms of downtime, recalls, damage to a company’s reputation, and more. For these reasons, chipmakers take customer returns very seriously, focusing resources to quickly get to the bot... » read more

Cutting IC Manufacturing Costs By Combining Data
By Anne Meixner - 11 Mar, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the benefits of incorporating financial data into fab floor decision-making, including what kind of cost data is most useful, with Dieter Rathei, CEO of DR Yield; Jon Holt, senior director of product management at PDF Solutions, Alex Burlak, vice president of advanced analytics and test at proteanTecs; and Dirk de Vries, techni... » read more

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