Toward Agentic Verification


Key Takeaways: Agentic verification provides flow orchestration for common repetitive tasks. Capabilities will expand when tools can learn from a larger context, including the specification. Design houses need to fully understand the costs and benefits and plan accordingly. Agentic verification is more than a buzzword. It is a pivotal moment in the evolution of verification ... » read more

Observability Is Essential For Modern Silicon


Experts At The Table: In-silicon observability — also known as on-die or on-chip visibility — is becoming increasingly important for managing the performance, reliability, and security of today’s high-performance systems. Semiconductor Engineering sat down to discuss this with Andy Nightingale, vice president of product management and marketing at Arteris; Nandan Nayampally, chief commerc... » read more

Faster Verification Debug With AI


Every stage of semiconductor development takes longer and requires more effort with each new generation of chips. At no stage is this more apparent than functional verification. Industry consensus is that verification consumes roughly two-thirds of development time and resources. Within verification, debug is the most challenging step, consuming a third to two-thirds of the effort. Any serious ... » read more

Curvilinear Masks Push The Limits Of Inspection And Metrology


Key Takeaways: Curvilinear masks require native data flows across design, mask data prep, writing, inspection, and metrology. Inspection is shifting from finding all defects to identifying which mask variations actually print on wafer. High-NA EUV will intensify inspection challenges, particularly for small printable defects and actinic contrast limits. Experts at the table:... » read more

Blog Review: May 27


Cadence's Igor Krause explains Precision Time Measurement (PTM), a PCIe feature that enables precise coordination of events across multiple components with independent local time clocks. Siemens' John McMillan suggests the way to achieve trusted traceability across the semiconductor supply chain is by implementing a blockchain-based distributed ledger paired with a secure digital twin. Sy... » read more

Multiphysics Fusion Technology for Multi-Die Designs Explained


Multiphysics issues are no longer a late-stage problem. Multi-die designs introduce tightly coupled electrical, thermal, electromagnetic, and electromechanical challenges that impact performance and reliability. This eBook shows why multiphysics analysis must move earlier in the design flow, and how a unified approach enables continuous validation from exploration through signoff. What You�... » read more

Chip Industry Week In Review


Advanced nodes and packaging AMD announced more than $10B in Taiwan ecosystem investments to scale advanced packaging manufacturing for AI infrastructure. The effort includes EFB-based 2.5D packaging collaborations with ASE and others. AMD also announced the start of its production ramp of its Venice processors on TSMC's 2nm process. Lam Research established a panel-level packaging cen... » read more

Beyond Ideal Crystals: The Case For Scale In Atomistic Modeling


Almost all computer simulations face the same trade-off: larger models can be more realistic and therefore more useful, but they also take longer to run. Engineers and scientists are therefore faced with an almost daily challenge of choosing a model that is detailed enough to capture the important details without making the calculation impractically expensive. "All models are wrong, but some... » read more

With Chiplets, What Role Does Economics Play?


Key Takeaways: For the data center, chiplet economics matter, but they’re not a primary decision-driver. With the exception of processor families, chiplets cannot address consumer markets today, where economics dominate. If a chiplet marketplace materializes, the economics may be friendlier because chiplets will have multiple customers and applications. Chiplets are notori... » read more

Mask Technology Faces A New Set Of Challenges


Key Takeaways: Mask inspection and repair remain the critical bottleneck, even as multi-beam writers have reduced mask-writing constraints. Curvilinear masks are becoming viable for critical layers, but qualification, metrology, and inspection standards still lag production needs. Scaling curvilinear requires curvilinear-native data flows, model-based checks, GPU/HPC compute, and les... » read more

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