Key Takeaways:
Photonics is pushing into the package and on-chip as leading-edge chipmakers look for ways to move more data faster and with less heat, but the manufacturing infrastructure needed to make that work is struggling to keep up.
For years, photonics occupied an unusual place in semiconductor roadmaps. Optical interconnects already carry enormous amounts of data across long distances, between data centers, and increasingly between racks inside them. But the more difficult transition has always been the final one — moving optics close enough to the compute engine so that electrical signals no longer have to travel significant distances across a board before being converted into light. The manufacturing challenges of integrating photonics are well understood, even though many remain unresolved, but the cost of leaving the optical engine at the edge of the system is becoming increasingly difficult to absorb.
“To bring the optical closer to the chip, or inside the chip, is a huge physical challenge, and I don’t think we really appreciate how difficult this is,” said Tien Wu, CEO of ASE, during his keynote at ECTC. “I once debated with my own people about whether I’d see it in my career. But this year we’re shipping silicon photonics in volume. It will take the next 20 years to make the methodology, the architectural design, and the automated process more efficient. At least we’re out of the gate.”
Fig. 1: Tien Wu, CEO of ASE presents the keynote at ECTC. Source: Semiconductor Engineering
Once optical engines move closer to logic, they become part of the same integration problem already pushing advanced packaging toward larger substrates, thinner die, finer pitches, and tighter process windows. Photonics introduces new constraints of its own, but it also forces the industry to solve together problems it could once treat separately, including warpage, alignment, thermal budget, and process margin. The pressure behind that convergence is a roadmap shifting faster than any single part of the supply chain can absorb.
“While we’ve been very successful helping the industry navigate the data-center, high-performance-computing roadmap, the next wave will be 10 times that,” Wu said. “And to get there takes new material, new processes, new power, new equipment, and new designs. Not a single company, not a single region, can do it alone.”
Moving data is becoming a system-level constraint
The immediate pressure to integrate photonics on-chip comes from the changing shape of AI infrastructure. The most useful unit of computation increasingly extends across a rack, a cluster, or an entire data center. At the same time, model size, inference demand, memory traffic, and the number of accelerators working together all increase the volume of data moving through the system. As that happens, the energy required to move bits begins to matter as much as the energy required to process them.
“What really drives performance today is not really the number of FLOPS, the teraFLOPS, or the petaFLOPS per GPU,” said Sandeep Razdan, director of process development engineering at Nvidia in a presentation at iMAPS. “It is rather the system architecture and the system performance as a whole.”
Co-packaged optics shortens the electrical path by moving the optical conversion much closer to the switching ASIC, which in some architectures can be measured in millimeters. That reduces the distance over which the highest-speed electrical signals have to travel and lowers the burden on the circuitry required to preserve signal integrity. The precise gains depend on architecture and generation, but the direction is clear. As networks grow, reducing the power required for each link creates savings that compound across the system.
Once that shift occurs, it is no longer sufficient to place logic, memory, and electrical interconnects into a well-controlled assembly. Optical engines, photonic ICs, electronic ICs, fiber arrays, external laser sources, thermal solutions, and mechanical structures must all operate together, and some of their requirements conflict.
The optical engine needs to be close to the ASIC to reduce electrical loss, but the ASIC is a major source of heat. Dense fiber arrays increase bandwidth but create handling, alignment, and test challenges. A package architecture that improves performance by bringing optics closer to logic may narrow the process window enough to create new yield problems. Nevertheless, the industry is moving forward because system requirements leave little room to wait for an ideal manufacturing flow.
“It’s not that integrated photonics has suddenly become manufacturable,” said Suresh Jayaraman, senior director of package development at Amkor. “It’s just that the performance requirements are driving the transition, and the industry is scrambling to get there.”
Where does the photonics problem belong?
The traditional division between front-end fabrication and back-end packaging is less useful as these systems become increasingly integrated. A photonic IC still begins as a front-end device. Waveguides, modulators, resonators, gratings, and couplers have to be patterned with enough precision to control loss and maintain consistent behavior across a wafer, because optical performance depends on the interaction between light and the physical geometry of the device.
That is one reason nanoimprint lithography has reappeared in discussions of photonic-chip manufacturing. Chinese startup Prinano reportedly said it has validated production of 200mm photonic-chip wafers using nanoimprint rather than conventional DUV, but that claim is difficult to evaluate without yield or defect-density data. Nevertheless, it’s technically interesting because some photonic structures rely on repeating nanoscale patterns more amenable to replication-based patterning than the irregular layouts of leading-edge logic. [1]
But a patterned photonic IC is only the beginning. It still needs to be connected to electronic ICs, optical fibers or waveguides, lenses, power delivery, and thermal-management structures. Those connections must hold alignment across process steps, thermal cycles, and the life of the device, and be assembled at a cost and throughput compatible with the systems they serve. The distinction matters because optical components introduce unfamiliar requirements in otherwise mature packaging flows.
“Because we are having to attach optical elements onto that PIC, those don’t behave as normal die,” said Jayaraman. “That’s something that has not been in our toolbox at all. We have to develop not just the process, but the expertise to do it.”
A front-end process can produce an excellent photonic device, but that does not guarantee it can be assembled economically, coupled efficiently, kept clean, thermally stabilized, inspected, and tested before more expensive components are added. A back-end process can reuse familiar substrates and attachment methods, but the tolerances are no longer governed only by electrical continuity and mechanical reliability. Optical loss can turn a small particle, a slight misalignment, or a local temperature change into a functional defect.
Some architectures attempt to move more of the optical integration into the substrate itself. One approach, presented at ECTC by Fumi Nakamura, researcher at the National Institute of Advanced Industrial Science and Technology (AIST), embeds photonic ICs in an organic substrate and uses single-mode polymer waveguides as an optical redistribution layer between the PIC and the optical connector. By eliminating direct fiber attachment at the PIC, providing pitch conversion, and integrating much of the optical path into the substrate before the electrical assembly flow is completed, the approach attempts to make photonic integration more compatible with established packaging processes.
The instinct to fit photonics into existing flows rather than build new ones around it reflects how the industry usually approaches high-volume manufacturing of an unfamiliar process. But perhaps a more plausible path would reuse the 2.5D and 3D platforms already developed for logic, memory, and interposer-based assemblies, and then identify the steps that no longer behave predictably once optical components are added. The package then becomes a hybrid manufacturing problem in the most literal sense. It combines front-end fabrication tolerances with back-end assembly constraints, then adds thermal, mechanical, optical, and test interactions that must be optimized simultaneously.
Heat changes the optical path
Thermal management becomes more complicated once optical engines are brought into the package, because heat affects more than reliability. An ASIC can tolerate a certain amount of temperature variation while still performing within its electrical specifications, but an optical path is sensitive to smaller changes in its physical environment. Refractive index, wavelength behavior, coupling efficiency, and insertion loss can all shift with temperature, which means the thermal design must protect the signal path and the device.
The architectural change sounds straightforward enough. The optical engine moves from the edge of the board closer to the switching ASIC, shortening the electrical path and improving efficiency. But the destination is also one of the hottest locations in the system, so the optical path now has to operate within a thermal environment largely created by the electronic devices beside it.
“Temperature change is one of the reasons why the shift of optical engines from the edge of the PCB to the package itself is taking a long time,” said Prahalad Parthangal, technical director for advanced packaging at Lam Research, during an IMAPS presentation. “It looks so simple. You just move the optical engine from the edge to the XPU or ASIC. But the XPU or ASIC generates tons of heat, and that starts to create problems within the optical path, where the refractive-index system changes and that leads to insertion losses. There are multiple layers and multiple locations where thermal management is going to be needed.”
Thermal analysis also has to begin earlier. It cannot be treated as a sign-off exercise after the optical, electrical, and package layouts have been largely fixed, because a problem discovered at that point may require changes across several domains. The package floorplan, the placement of the optical engines, the routing of electrical paths, the mechanical structure, and the heat-removal strategy all affect one another. The design flow has to reflect those interactions before the physical package exists.
“Photonics is very sensitive to heat, so thermal becomes even more important,” said Amlendu Shekhar Choubey, senior director of product management at Synopsys. “Doing a full-stack thermal analysis becomes very important. You need to have an integrated flow where your optical simulation and electrical simulation can coexist, and then a design platform where you can integrate your electronic design, advanced packaging, and your optical PIC design, so that you can co-design all these components from architecture space to final sign-off together.”
That becomes more difficult as package sizes increase and optical engines multiply around the ASIC. Larger assemblies are more susceptible to warpage and mechanical stress, while dense optical channels introduce more potential sources of thermal crosstalk. The system-level benefit of bringing optics closer to logic remains compelling, but the thermal solution must be designed into the architecture from the outset.
Materials and cleanliness compound photonics manufacturability
The materials stack also becomes more consequential as packages grow thinner, larger, and more heterogeneous. Carrier wafers, temporary-bonding layers, molding compounds, and encapsulants each change how the structure responds to heat and mechanical stress, and warpage is the clearest example. When the CTE of the carrier and the package do not match closely enough, the structure deforms across thermal cycles in ways that accumulate from one process step to the next.
Contamination control also changes once optical components are added. Electronic packages already require clean processes, but photonics creates failure mechanisms that may be triggered by particles or residues too small to matter in a conventional electrical path. A contaminant that would once have been a process nuisance can become a functional defect if it sits inside an optical cavity or interferes with a lens array.
“The light can get easily attenuated by contamination,” said Jayaraman. “For normal electronic ICs, that level of cleanliness was okay, but now we’re seeing that even one small particle in those cavities where the micro-lens arrays sit can matter. Those have to be really pristine clean.”
The same intolerance shows up at the bonding interfaces beneath those optical structures, where a residue thin enough to be invisible can still break a connection.
“If that layer is actually coated with a monolayer of polymer — just a molecule, a bunch of chains — even that will affect the way your solder wets the pad,” said Hamed Derami, technology strategist for advanced packaging at Brewer Science. “That’s going to change your electrical performance, your delamination, your breakage. That’s going to affect everything else.”
That sensitivity reaches across the flow into the cleaning chemistry, residue removal, and particle inspection, which have to protect optical surfaces before attachment and verify them while cavities and coupling structures are still accessible. How the industry measures and inspects those interfaces at production scale is a test-and-metrology problem in its own right.
Test has to move earlier
Test insertions become the points at which the economics of the entire flow are exposed. A photonic IC, an electronic IC, an optical engine, a substrate, and a fiber interface may each represent substantial value before they are assembled together. If a failure is discovered only after the full package is complete, the cost of the defect includes every good component already committed to the assembly.
The logic of known-good die, therefore, has to expand. Manufacturers increasingly need confidence in the PIC, the optical attachment, the coupling efficiency, and the optical path before the most expensive electronic dies are added, which creates pressure for intermediate optical test insertions, even when those additions increase process time and require new equipment.
“Before you go and attach the EICs, let’s do a test of the optics to make sure that we are not committing the EIC die to locations where the optics are not working well or the attenuation is too significant,” said Jayaraman. “The test flow is going to become more complicated. There’s going to be more test insertions.”
Optical test also introduces measurements that do not fit neatly into conventional electrical test flows. Wavelength drift, optical power, attenuation, and coupling losses have to be measured alongside electrical behavior, and light has to be introduced into the structure and collected from it, often when the package is not yet complete. Probe strategies, fixtures, sockets, and instrumentation all have to evolve as optical test moves further upstream.
The scale of AI systems makes that problem more demanding. Optical links are multiplying across packages, racks, and systems, and measuring one component in a controlled development environment is very different from screening thousands of optical and electrical channels at production speed.
“Testing photonics and electronics together is very challenging, especially at the scales that I’m describing,” said Nvidia’s Razdan. “We are dealing with thousands of optical and electrical channels per chip and per system, and these have to be tested at a very large scale, at a very high volume. Advanced testing platforms are what’s really needed in order to enable these systems in the future.”
Earlier screening improves the economics even when the test flow becomes more complicated. It may add time and equipment cost at intermediate steps, but those costs have to be weighed against the value of a completed module that fails after several expensive components have already been integrated. The cheapest test is not always the one with the lowest cost per insertion. It may be the one that prevents a marginal component from consuming additional value downstream.
“Cost is another issue,” said Scott Carroll, senior director of test business development at Amkor. “The more you can do at the probe level to eliminate the defects, the better off you’re going to be.”
Design infrastructure and equipment have to evolve
The manufacturing challenge is not confined to the package flow. It also affects the design infrastructure that defines the product and the equipment ecosystem that builds it. Foundries, OSATs, EDA companies, materials suppliers, equipment vendors, and system designers all need information from one another, but the industry is still early in defining which data must move between them and in what form.
Advanced-package design kits are beginning to serve a role analogous to front-end PDKs, though the required information is broader: thermal models, mechanical properties, material properties, and optical constraints increasingly have to travel with the package definition, and some of that data has not yet been characterized in a form usable across design flows.
Those kits matter because they are what an automated design flow runs on. Once the number of interacting variables exceeds what an engineering team can track by hand, the work has to be automated, and automation depends on having design rules and standardized collateral in a form a tool can consume. Without them, there is nothing for the flow to act on.
“That has been a bottleneck in mass adoption of multi-die design, because you need design rules, you need collaterals to automate this process,” said Choubey. “This whole technology cannot scale if there’s not a high level of automation similar to what we see in more established silicon processes.”
Equipment suppliers face a related problem. A tool optimized for one customer’s architecture may not transfer to another’s if the optical interface, cavity structure, attachment method, or cleaning sequence changes. Photonics forces equipment vendors to revisit process assumptions that once seemed stable, so development tools may need to evolve iteratively, with early systems establishing design targets that later generations of equipment can refine.
The industry is unlikely to converge immediately on a single photonics/electronics architecture. Some systems will adapt 2.5D platforms, while others will use more aggressive 3D integration, embedded PICs, polymer waveguides, external laser sources, or alternative front-end patterning methods. Several paths may remain viable because the right choice depends on the application, bandwidth, distance, thermal budget, package geometry, and cost structure.
Conclusion
The central manufacturing problem is no longer whether photonics can be integrated with advanced semiconductor systems. That question has already been answered in multiple forms, from co-packaged optical switches to embedded PICs and polymer-waveguide routing. The harder question is whether those systems can be built reliably at scale, inspected at the right points, and tested before too much value has been committed to a marginal assembly. It’s a challenge that crosses boundaries the industry has traditionally treated as separate. Front-end film quality affects optical performance, package materials affect warpage and alignment, and cleaning chemistry affects both optical loss and downstream bonding. In addition, thermal behavior can change the signal path itself.
Part of the impetus to solve these problems comes from the limits of scaling elsewhere. As the industry approaches the physical limits of lithography, packaging increasingly bears the burden of system-level performance, and photonics is one of the tools it turns to.
“There is a physical limit on lithography,” said Tien Wu, CEO of ASE. “The industry is probably 5 to 10 years from that point. Packaging, as a system integrator — the VRM, photonics — these are some of the tools to solve that system integration and optimization.”
The likely outcome is not a single winning architecture or one decisive breakthrough. Manufacturable photonics will emerge from a sequence of smaller improvements that allow the entire stack to behave more predictably. This includes better models, tighter materials windows, cleaner interfaces, earlier test insertions, more complete design kits, and equipment built around clearer process guardrails. Optics is moving closer to logic because system economics increasingly require it. The work now is making the manufacturing flow mature enough to follow.
Reference
Related Articles
Co-Packaged Optics Testing Faces Steep Data Center Ramp
Scaling to tens of millions of CPO units per year requires the industry to first settle on automated, cost-effective methods for electrical and optical testing.
Packaging Technologies Redefine AI And HPC Scalability Limits At ECTC 2026
Advancements in EMIB-T, co-packaged optics, and glass substrates.
The Sub-2nm Paradox
Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.
 |
 |
 |
 |
 |
 |
 |  |
 |
 |
 |
Leave a Reply