Orbital Data Centers Are Souped-Up Satellites – For Now


Key Takeaways: Today’s orbital data centers are better described as compute centers in space, as they resemble satellite constellations more than terrestrial data centers. The most common power solution is sun-synchronous solar at the poles, but this requires a multi-hop data relay from power-hungry compute to standard satellite constellations in the low-orbit mesh, then to Earth. ... » read more

Keeping Security Algorithms Current Is Getting Harder


Key Takeaways: Keeping security algorithms current is now a lifecycle challenge that spans chip design, manufacturing, deployment, and long-term maintenance across the supply chain. To stay ahead of emerging threats — especially post-quantum risks — hardware must be built with cryptographic agility, secure roots of trust, and reliable update mechanisms from the start. The bigge... » read more

AI-Defined Vehicles Increase Pressure On Auto Ethernet Reliability


Key Takeaways: For AI-defined vehicles and onboard agentic AI, Automotive Ethernet provides high bandwidth for sensor data fusion, TSN ensures low latency and synchronization for real-time decisions, and MACsec secures the data link. Time-sensitive networking (TSN) is an essential protocol for ensuring 10BASE-T1S delivers data to where it needs to go on time. Still, it becomes less esse... » read more

Delivering Automotive-Grade Quality With Customized FinFET Foundation IP


By Andrew Appleby, Daryl Seitzer, and Nafiz Ahmed The growing compute demands of modern vehicles are forcing chipmakers to venture into new territory. To deliver increased processor performance for engine and body control systems, one leading semiconductor supplier knew it had to move to an automotive-qualified FinFET technology process — a leap that would introduce significant new desi... » read more

Blog Review: Jun. 3


Siemens' Gordon Allan contends that verification IP gives design teams a practical way to verify standards-based interfaces and memories without rebuilding the same infrastructure generation after generation and shares key evaluation metrics. Synopsys' Sutirtha Kabir suggests that successful multi-die design will require deeper collaboration from early architecture exploration to manufacturi... » read more

1 Megawatt Racks In Data Centers


The demand for performance in an AI data center is causing a huge spike in the amount of power being consumed. Within a rack are a half-dozen SoC components housed in different types of advanced packages and connected with an assortment of blazing-fast interface IP and optical signaling. Manmeet Walia, director of product management for mixed-signal PHY IP in the Synopsys Solutions Group, talks... » read more

Beating the Edge AI Power Wall with Low Voltage Foundation IP


Edge AI is pushing the limits of power efficiency as intelligence moves closer to the data source. Designing for ultra-low voltage operation is now essential to achieve optimal performance-per-watt—but it introduces significant complexity in modeling, variation, and design predictability. In this white paper, discover how a unified, silicon-proven Foundation IP platform approach enables relia... » read more

The Sub-2nm Paradox


Key Takeaways: Process variation and physics are changing semiconductor design, manufacturing, and economics at 2nm and below. Even though new manufacturing processes are being introduced, it's taking longer for them to mature. The focus for many chip designs is faster data movement and more efficient computing, rather than just relying on more transistors per mm2. At 2nm an... » read more

Chip Industry Week In Review


ECTC Panel-level packaging, hybrid bonding, new substrates, and fine-pitch interconnects topped the list of advanced packaging technologies at ECTC this week. Among the announcements: ASE launched an automated 310mm × 310mm panel-level packaging production line. Expected to enter production in the first half of 2027, the line is compatible with FOCoS and FOCoS-Bridge pa... » read more

Swapping Out Chiplets: I/Os Vs. Compute


Key Takeaways: Companies can save time and money by swapping out a compute, memory, or I/O chiplet to gain technology improvements, while keeping the other dies stable. Chip architects may choose to keep their I/Os stable and swap out compute to move from a 5nm process node to 3nm to achieve performance and power improvements, or swap out memory from LPDDR5X to LPDDR6. Swapping out... » read more

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