Blog Review: Sept. 18

By Jesse Allen - 18 Sep, 2024 - Comments: 0

Siemens’ Kyle Fraunfelter explores the similarities between hurricane forecasting and semiconductor manufacturing to argue for the value of integrating real-time wafer fabrication measurements into the digital twin models used to simulate the semiconductor fabrication process. Cadence’s Rohini Kollipara introduces Display Stream Compression (DSC), which can enable higher resolutions and ... » read more

CXL Thriving As Memory Link

By Karen Heyman - 16 Sep, 2024 - Comments: 0

CXL is emerging from a jumble of interconnect standards as a predictable way to connect memory to various processing elements, as well as to share memory resources within a data center. Compute Express Link is built on a PCI Express foundation and supported by nearly all the major chip companies. It is used to link CPUs, GPUs, FPGAs, and other purpose-built accelerators using serial communic... » read more

Chip Industry Week In Review

By The SE Staff - 13 Sep, 2024 - Comments: 0

Infineon rolled out the world's first 300mm gallium nitride (GaN) wafer, opening the door for high-volume manufacturing of GaN-based power semiconductors. A 300mm wafer contains 2.3 times as many chips per wafer as a 200mm wafer. Fig.1: Infineon's 300mm GaN wafer. Source: Infineon The Semiconductor Industry Association released its 2024 State of the U.S. Semiconductor Industry report th... » read more

Simulation Replay Tackles Key Verification Challenges

By Robert Ruiz - 12 Sep, 2024 - Comments: 0

Simulation lies at the heart of both verification and pre-silicon validation for every semiconductor development project. Finding functional or power problems in the bringup lab is much too late, leading to very expensive chip turns. Thorough simulation before tapeout, coupled with comprehensive coverage metrics, is the only way to avoid surprises in silicon. However, the enormous size and comp... » read more

Is PPA Relevant Today?

By Brian Bailey - 12 Sep, 2024 - Comments: 1

The optimization of power, performance, and area (PPA) has been at the core of chip design since the dawn of EDA, but these metrics are becoming less valuable without the context of how and where these chips will be used. Unlike in the past, however, that context now comes from factors outside of hardware development. And while PPA still serves as a useful proxy for many parts of the hardwar... » read more

Higher Density, More Data Create New Bottlenecks In AI Chips

By Adam Kovac - 12 Sep, 2024 - Comments: 0

Data movement is becoming a bigger problem at advanced nodes and in advanced packaging due to denser circuitry, more physical effects that can affect the integrity of signals or the devices themselves, and a significant increase in data from AI and machine learning. Just shrinking features in a design is no longer sufficient, given the scaling mismatch between SRAM-based L1 cache and digital... » read more

Blog Review: Sept. 11

By Jesse Allen - 11 Sep, 2024 - Comments: 0

Cadence's Neha Joshi introduces the IEEE 1801 standard, also known as UPF (Unified Power Format), which offers a uniform framework for defining power domains, power states, and power intent to ensure consistency across diverse tools and phases of the design process. Siemens' John McMillan warns that known good die may not behave the same in 3D-ICs as they do standalone and suggests that mult... » read more

Taking Data Center Serviceability To The Next Level

By Nozar Nozarian - 10 Sep, 2024 - Comments: 0

It is no secret that Artificial Intelligence (AI) workloads are driving an exponential growth in the scale of supercomputers and data centers. Training the latest LLM (Large Language Model), for instance, typically requires thousands of specialized processing cores running at full speed. As these models get more advanced with each generation, they need additional compute performance to absorb a... » read more

Promises and Perils of Parallel Test

By Anne Meixner - 10 Sep, 2024 - Comments: 1

Testing multiple devices at the same time is not providing the equivalent reduction in overall test time due to a combination of test execution issues, the complexity of the devices being tested, and the complex tradeoffs required for parallelism. Parallel testing is now the norm — from full wafer probe DRAM testing with thousands of dies to two-site testing for complex, high-performance c... » read more

Standardizing Defect Coverage In Analog/Mixed Signal Test

By Gregory Haley - 10 Sep, 2024 - Comments: 0

A newly drafted IEEE standard will bring more consistency to defect metrics in analog/mixed (AMS) designs, a long-overdue step that has become too difficult to ignore in the costly heterogeneous assemblies being deployed inside of data centers and mobile devices. Standardizing analog is no simple feat due to the legacy approach to AMS design, and this is not the first attempt at improving te... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.