Chip Industry Week in Review

By The SE Staff - 15 May, 2026 - Comments: 0

Global The U.S. created a licensing path for Nvidia H200 shipments in January and has since approved sales to 10 Chinese companies, but so far no shipments have been confirmed, reports Reuters. With a looming end-of-year expiration, SIA, SEMI, and other business groups are urging Congress to extend the US semiconductor tax credit and expand it to cover semiconductor design and other act... » read more

Chiplets Need A New Workflow

By Ann Mutschler - 14 May, 2026 - Comments: 0

Key Takeaways: Chiplet design turns semiconductor development into a system-level problem, requiring coordinated workflows across design, packaging, verification, test, and reliability. Successful chiplet workflows must handle multi-physics challenges — especially thermal, mechanical, power, and signal integrity — early enough to reduce costly failures before assembly and tape-out. ... » read more

Flash Getting Stacked High-Bandwidth Version

By Bryon Moyer - 14 May, 2026 - Comments: 1

Key takeaways: A new HBF 3D flash stack is similar to HBM for use in AI processing. HBF capacity will be much higher, allowing static storage of AI model weights, with optimized read speed. Samples are due out later this year, with accelerators featuring it coming out next year. AI inference using modern models requires billions of parameters, and moving them to where they c... » read more

Gates Add Functionality, But Wires Create Problems

By Brian Bailey - 14 May, 2026 - Comments: 0

Key takeaways: While transistors see continuous improvement, wires keep getting worse because of the smaller geometries and larger chip sizes. There are limited ways to avoid such problems, but the biggest impact will come from floorplanning. Analysis today is not adequate. New developments, such as backside power and 3D integration, provide temporary relief but new materials are a d... » read more

Scaling PCIe Controllers for AI Bandwidth: A Multistream Architecture Analysis for 64 GT/s and 128 GT/s

By Synopsys - 13 May, 2026 - Comments: 0

Scaling raw lane speed without rethinking controller microarchitecture leads to diminishing returns. It introduces multistream architecture, a controller‑level re‑architecture designed to sustain effective bandwidth under mixed and small‑packet workloads. This paper examines the architectural inflection point at PCIe 6.0, details transmit‑ and receive‑side changes required for multist... » read more

Blog Review: May 13

By Jesse Allen - 13 May, 2026 - Comments: 0

Siemens' Loay Hegazy, Mohamed Taher, and Sherif Hammouda describe a GPU rasterizer designed specifically for computational lithography and present benchmark results and practical implications for mask synthesis workflows. Cadence's Udaya Shankar introduces RTL, logic, and physical restructuring techniques and how they can help improve PPA, reduce dynamic power consumption, and optimize place... » read more

Supporting Safety Requirements from RTL Exploration Through Implementation in Semiconductor Devices (Politecnico di Torino, Synopsys)

By Technical Paper Link - 12 May, 2026 - Comments: 0

A new technical paper, "Early Functional Safety and PPA evaluation for faster digital design development," was published by researchers at Politecnico di Torino and Synopsys. Abstract "The use of semiconductor devices in safety-critical applications is increasing in both volume and complexity. Applications in markets such as automotive, data centers, and aerospace have dependability requi... » read more

Complete End-To-End Closed-Loop Product Yield Ramp And Learning

By Guy Cortez - 12 May, 2026 - Comments: 0

By Guy Cortez and Maheshwaran Jothi Yield ramp has always been a concern in semiconductor manufacturing: systems companies need confidence that devices meet quality targets before shipment, and chipmakers need to reach yield entitlement quickly to control cost and supply. While this has never been easy, advanced nodes are raising the bar again. First, designs are larger and more heterogen... » read more

AI Accelerator Testing Depends On DFT Innovations

By Laura Peters - 12 May, 2026 - Comments: 0

Key Takeaways: I/O and lane repair capabilities are becoming critical to improving yield. System-level testing catches marginal defects and rare defects such as silent data corruption errors. Synopsys and TSMC developed a multi-die demo vehicle capable of full test, monitor, debug, and repair capability across the system’s lifecycle. The proliferation of accelerators in AI... » read more

HBM Shifts Testing Left To Preserve AI Chip Yield

By Anne Meixner - 12 May, 2026 - Comments: 1

Key Takeaways: A high-yield, known-good stack requires multiple test insertions. Known good stack testing poses challenges for power delivery and thermal management. The shift to HBM4 and HBM5 will increase the pressure for shift-left test flows. Taller high-bandwidth memory (HBM) stacks and tighter TSV pitch are impacting AI module yields. The solution is to push test furth... » read more

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