tag: Synopsys

Securing AI at the Silicon Level: Solutions for a Smarter, Safer Future
By Synopsys - 06 May, 2026 - Comments: 0

This white paper explains how Synopsys Security IP embeds hardware‑rooted protection into AI SoCs and chiplets to secure their data and models. It highlights growing AI attack vectors across edge and data‑center environments and shows how technologies like PUF, tRoot HSM, interface security, and PQC create long‑term, silicon‑level trust. Why read this whitepaper: Learn how sili... » read more

Using AI To Monitor Dashboards In Chips And Systems
By Ed Sperling - 06 May, 2026 - Comments: 0

Key Takeaways: New types of dashboards are being used in conjunction with AI to make sense of large quantities of data. These dashboards can be used to quickly identify and fix power and heat-related problems, such as hotspots or voltage droop. Future dashboards will likely be much more customizable for different users or applications. Chipmakers are starting to use AI to ma... » read more

Designing Chips In The Context Of Rapidly Evolving AI
By Ann Mutschler - 04 May, 2026 - Comments: 0

Key Takeaways: Agentic edge AI drives long-lived, tool-mediated loops with variable demands for compute, tokens, and memory. Edge PPA is dominated by memory hierarchy and data movement, forcing tight feature triage and robust RAS. Rapid model churn (multimodal, MoE, new formats) requires programmable, headroom-rich compute, interconnect, and runtime. Experts At The Table: Ch... » read more

Chip Industry Week in Review
By The SE Staff - 01 May, 2026 - Comments: 0

Advanced nodes and capacity The US Commerce Dept. told IC equipment makers to stop shipments to Hua Hong Group, China's No. 2 chipmaker, in order to protect America's lead, according to Reuters. Global AI competition is causing wafer and packaging shortages, but capacity increases are expected to come online later this year and in 2027 to ease the crunch, according to TrendForce. Leadi... » read more

Creating Agentic EDA Methodologies
By Brian Bailey - 30 Apr, 2026 - Comments: 1

Key takeaways Agentic methodologies need to be able to reason across multiple data formats and abstractions. It is not clear how much data from previous designs is useful in new designs. Standards may help, but the lack of them may only impact cost. The relationship between tools and methodologies is bidirectional. Tools enable methodologies, and methodologies are dependent ... » read more

Foundry Capacity Is Limiting Who Competes At Leading Edge Nodes
By Ann Mutschler - 30 Apr, 2026 - Comments: 0

Key Takeaways: Leading-edge node access is increasingly reserved for hyperscalers, squeezing smaller chip developers. Chiplets and advanced packaging offer a path forward, but raise cost, complexity, and risk — especially for smaller teams. Chip architecture is now driven as much by capacity, yield, and economics as by technical goals. The benefits of device scaling are sl... » read more

Solving Clock Signal Integrity And Jitter Issues
By Manoz Palaparthi - 30 Apr, 2026 - Comments: 0

A recent blog post discussed the challenges of clock signal integrity and clock jitter in deep submicron semiconductor devices. Nice, clean clock signals are degraded due to many factors, including noise in the power delivery network (PDN). Timing variation due to clock jitter is also a serious issue, especially for chips operating at low voltage with high frequencies. The impact due to cloc... » read more

NoC Coherency Challenges Balloon With AI SoCs And Chiplets
By Liz Allan - 30 Apr, 2026 - Comments: 0

Key Takeaways Data movement, congestion, and energy efficiency are key determiners of whether compute is usable. Different processors bring various coherency challenges. For example, a cache-coherent NoC for CPUs is expensive and harder to verify than an I/O-coherent NoC for an accelerator. Designers need to balance top-down performance with bottom-up physical engineering to effect... » read more

How Long Will CAN Stick Around As Rival Networks Speed Up?
By Liz Allan - 29 Apr, 2026 - Comments: 0

Key Takeaways Automotive Ethernet is rapidly becoming the backbone of software-defined vehicles for higher bandwidth, scalability, and advanced features like TSN and security that legacy protocols cannot match. CAN, LIN, and other legacy networks will not disappear quickly because they are deeply embedded, low‑cost, and proven, but they are increasingly seen as inadequate for future A... » read more

Blog Review: Apr. 29
By Jesse Allen - 29 Apr, 2026 - Comments: 0

Synopsys' Madhumita Sanyal shows why interface IP has emerged as the keystone for building scalable, reliable 3D multi-die designs in which interconnects often have a greater influence on overall system capability than the peak performance of individual dies. Cadence's Frank Ferro checks out why SOCAMM2 built on LPDDR is being deployed in AI data centers, increasing memory bandwidth and capa... » read more

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