Blog Review: May 27


Cadence's Igor Krause explains Precision Time Measurement (PTM), a PCIe feature that enables precise coordination of events across multiple components with independent local time clocks. Siemens' John McMillan suggests the way to achieve trusted traceability across the semiconductor supply chain is by implementing a blockchain-based distributed ledger paired with a secure digital twin. Sy... » read more

Multiphysics Fusion Technology for Multi-Die Designs Explained


Multiphysics issues are no longer a late-stage problem. Multi-die designs introduce tightly coupled electrical, thermal, electromagnetic, and electromechanical challenges that impact performance and reliability. This eBook shows why multiphysics analysis must move earlier in the design flow, and how a unified approach enables continuous validation from exploration through signoff. What You�... » read more

Chip Industry Week In Review


Advanced nodes and packaging AMD announced more than $10B in Taiwan ecosystem investments to scale advanced packaging manufacturing for AI infrastructure. The effort includes EFB-based 2.5D packaging collaborations with ASE and others. AMD also announced the start of its production ramp of its Venice processors on TSMC's 2nm process. Lam Research established a panel-level packaging cen... » read more

Beyond Ideal Crystals: The Case For Scale In Atomistic Modeling


Almost all computer simulations face the same trade-off: larger models can be more realistic and therefore more useful, but they also take longer to run. Engineers and scientists are therefore faced with an almost daily challenge of choosing a model that is detailed enough to capture the important details without making the calculation impractically expensive. "All models are wrong, but some... » read more

With Chiplets, What Role Does Economics Play?


Key Takeaways: For the data center, chiplet economics matter, but they’re not a primary decision-driver. With the exception of processor families, chiplets cannot address consumer markets today, where economics dominate. If a chiplet marketplace materializes, the economics may be friendlier because chiplets will have multiple customers and applications. Chiplets are notori... » read more

Mask Technology Faces A New Set Of Challenges


Key Takeaways: Mask inspection and repair remain the critical bottleneck, even as multi-beam writers have reduced mask-writing constraints. Curvilinear masks are becoming viable for critical layers, but qualification, metrology, and inspection standards still lag production needs. Scaling curvilinear requires curvilinear-native data flows, model-based checks, GPU/HPC compute, and les... » read more

Options Grow For Standardizing Data Movement And Sharing Resources


Semiconductor Engineering sat down to discuss memory interfaces, interconnects, and memory access scaling with Madhumita Sanyal, senior director of technical product management at Synopsys; Swadesh Choudhary, senior principal engineer at Intel; Siamak Tavallaei, senior principal engineer at Samsung SSI; and Mohsen Asad, senior director of technology at Credo. What follows are excerpts of a disc... » read more

Blog Review: May 20


Cadence's Siddh Virani demonstrates how to import and integrate foreign language logic into PSS on both Target and Solve platforms, opening possibilities for code reuse and cross-language collaboration. Synopsys' Sumit Vishwakarma finds that AI model training and inference workloads are forcing the industry to rethink not only how much compute fits in a rack, but how servers are architected ... » read more

Chip Industry Technical Paper Roundup: May 19


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Micro-Transfer Printing on Silicon Photonics: Tutorial, Recent Progress and Outlook 🔗 Ghent U., imec Challenges and prospects of 2D electronics for future monolithic CFETs 🔗 SKKU, Hanyang U. et al. A Device-Physics-Informed Artific... » read more

Confusion Grows With More Interconnect Options And Tradeoffs


Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

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