AI Accelerators Usher In New Era For IC Test


Key Takeaways The parallelism in AI accelerators enables low latency but complicates failure isolation. HBM can account for 50% of package cost, so known-good stack assurance is critical. DFT and test cooperate to solve final test, singulated die test, SLT, and in-system test for data centers. AI accelerators are used for everything from training large language models to mak... » read more

Untrusted Analog Components Add Risks For Critical Infrastructure


Key Takeaways New certificate-based solutions are necessary within fabs and packaging houses to deliver trusted semiconductors. Physical IDs bind the device to the certificate, but it needs to be immutable and unclonable. Extrinsic IDs are required for analog, mixed-signal, sensor ICs as well as discrete components. Rising concern over the source and destination of chips, an... » read more

World First: MACsec IP Receives ISO/PAS 8800 Certification For Automotive And Physical AI Security


The automotive industry is entering the age of physical AI. Vehicles are rapidly transforming into intelligent, software-defined systems that perceive their environment, make real-time decisions, and act in the physical world. As autonomy expands and AI workloads move to the edge, one reality is becoming clear: If the data cannot be trusted, the AI cannot be trusted. Following independent... » read more

Moving Electrons, Not Just Vehicles


Key Takeaways: There are several ways to convert AC power from the grid to DC power in the system. Some degrade the battery faster than others. Battery management systems monitor cell voltage, current, and temperature, helping to estimate state of charge, health, and useful remaining life. A PMIC with a multi-level converter is the most efficient way to get power from the battery to ... » read more

IC Security Threats Spike With Quantum, AI, And Automotive


Key Takeaways: The top challenge for the chip architect is building post‑quantum cryptography securely into real hardware from the start, not just selecting approved algorithms. Security must be treated as a core silicon architecture decision early on, especially for long‑lived, automotive, and multi‑vendor systems. Automotive cybersecurity now requires a holistic approach span... » read more

The One Bit Problem That Can Break a System


Key Takeaways: Bit flipping is no longer a rare reliability issue but a systemic risk driven by shrinking process nodes, higher clock speeds, lower voltages, and radiation exposure, leading to silent data corruption and potential system failure. The same mechanisms that cause accidental bit flips can be deliberately exploited through techniques such as clock, voltage, laser, and rowhamm... » read more

Accelerating Automotive Innovation: SRAM Compiler Breakthroughs for 5nm and 3nm SoCs


Modern automotive SoCs must deliver extreme performance, functional safety, and long‑term reliability — all under growing power and thermal constraints. This white paper explains how next‑generation Synopsys SRAM Compiler IP for TSMC N5A and N3A helps design teams meet these challenges with measurable gains in PPA, reliability, and system robustness. Why Read this White Paper: See... » read more

Blog Review: April 1


Siemens EDA's Harry Foster considers why first-silicon success is continuing to decline even though tools are capable of handling much larger design sizes and identifies how increasingly complex interactions between components cause traditional verification assumptions to break down. Synopsys' Eldo N Baby explores dynamic voltage drop analysis, including how to bring in switching scenario in... » read more

AI’s Potential And Limitations In Chip Design


Experts at the Table: Semiconductor Engineering sat down to discuss the opportunities and challenges of using AI in chip design, with Thomas Andersen, vice president for AI & Machine Learning at Synopsys; Sridhar Boinapally, senior director of analog/mixed signal tools/flow at Intel; Alex Starr, corporate fellow at AMD; Stuart Oberman, vice president for GPU hardware engineering at Nvidia; ... » read more

Chip Industry Technical Paper Roundup: Mar. 31


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips 🔗 ETH Zurich, Rutgers University Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review 🔗 Univ... » read more

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