tag: Synopsys

Challenges In Scaling Chips To 2nm And Below
By Ed Sperling - 30 Mar, 2026 - Comments: 0

Key Takeaways Scaling to 2nm and below continues due to power improvements per watt, but progress is much more challenging and costly. Solutions to problems often create other problems due to less margin for tradeoffs, often requiring larger interposers, more chiplets, and more complex packages. New levels of precision are required throughout the design-through-manufacturing flow, re... » read more

Chip Industry Week In Review
By The SE Staff - 27 Mar, 2026 - Comments: 0

Arm uncorked its first internally developed CPU chip this week, aimed squarely at the agentic AI data center market. Arm CEO Rene Haas (pictured) emphasized the CPU's power efficiency and performance/watt compared to other AI processor architectures. "We are obsessed with efficiency, and if you think about one of the biggest appeals that Arm has had over the years, it is power profile," he ... » read more

IP Requirements Evolve For 3D Multi-Die Designs
By Madhumita Sanyal - 26 Mar, 2026 - Comments: 0

As Moore’s Law continues to slow and demand for compute density and bandwidth accelerates, the semiconductor industry is rapidly shifting from monolithic SoCs to 3D multi-die designs. While 2.5D integration has extended system scaling, it is no longer sufficient to meet the bandwidth, latency, and power requirements of AI, HPC, and advanced automotive applications. The move to true 3D multi-d... » read more

Memory Wall Gets Higher
By Brian Bailey - 26 Mar, 2026 - Comments: 1

Key Takeaways An increasing percentage of the chip area is consumed by the same amount of SRAM for each node shrink. The problem is not limited to leading-edge AI, as it will eventually impact even small MCUs and MPUs. Architectural changes may be required. Stacking SRAM chiplets on logic is possible but expensive. SRAM is a vital piece of all computing systems, but its fail... » read more

Data Boom Puts Pressure On NoCs, Fabrics
By Liz Allan - 26 Mar, 2026 - Comments: 0

Key Takeaways: NoC challenges, such as wiring congestion, timing closure, and performance, must be considered in tandem with topology and placement. Topologies can be customized to meet an application’s specific data flow needs, with a system containing multiple topologies to suit different data or zones. What is challenging for one type of system, such as an SoC, switch, or AI chi... » read more

AI Won’t Kill Verification IP, But It Will Redefine It
By Ann Mutschler - 26 Mar, 2026 - Comments: 0

Key Takeaways AI will enhance, not replace, verification IP by automating test generation and debug. Verification IP’s core value will increasingly lie in trust, accountability, and system-level realism, especially as designs become more complex, multi-die, and security-sensitive. AI shifts verification bottlenecks from execution to specification quality, raising expectations for c... » read more

Beating The Heat In 3D Packages
By Laura Peters - 25 Mar, 2026 - Comments: 0

Key Takeaways: Thermal management is a central design constraint, requiring early, thorough planning. Accurate thermal simulation requires AI-driven adaptive meshing and real-world validation. Innovative STCO strategies can drastically reduce GPU peak temperature. As HPC and AI accelerators push power densities to 1kW and beyond, the heat generated by rapidly switching tran... » read more

Blog Review: Mar. 25
By Jesse Allen - 25 Mar, 2026 - Comments: 0

Synopsys' Jayraj Nair checks out how a model-based systems engineering workflow can help manage the complex multiphysics analysis needed to optimize heterogeneous systems. Siemens' Melville Bryant explains the difference between semiconductor traceability and tracking and why they're both essential, especially for complex multi-die devices. Cadence's Jamdagni Trivedi checks out VIP option... » read more

Building an AI Chip: Security, Software Development, and Lifecycle Management
By Synopsys - 25 Mar, 2026 - Comments: 0

The third white paper in our series, "Building an AI Chip" delves into the critical aspects of ensuring robust security and efficient software development for AI chips. As AI applications become increasingly integrated into everyday systems, the need for secure and reliable chip designs is paramount. This paper outlines essential strategies for safeguarding AI chip development, optimizing softw... » read more

Auto Ethernet 10BASE-T1S Steps Up, With Tbps On The Horizon
By Liz Allan - 23 Mar, 2026 - Comments: 0

Key Takeaways: Automotive Ethernet, particularly 10BASE-T1S, is emerging as a replacement for CAN in vehicle networks, with higher speeds anticipated for future autonomous and connected cars. The transition to Ethernet in automotive domains is not universal; some OEMs may retain CAN or LIN in certain areas due to cost, and integrating various Ethernet standards can be technically feasib... » read more

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