tag: TSVs

What’s Next For Memory?
By Mark LaPedus - 14 Aug, 2014 - Comments: 4

Apple, Samsung and others are developing the next wave of smartphones and tablets. OEMs want to integrate new memory schemes that provide more bandwidth at lower power. But there are some challenges in the arena that are prompting memory makers to rethink their mobile DRAM roadmaps. The conventional wisdom was that memory makers would ship mobile DRAMs based on the new LPDDR4 interface stand... » read more

When Will 2.5D Cut Costs?
By Brian Bailey - 07 Aug, 2014 - Comments: 2

There is a constant drive to reduce costs within the semiconductor industry and, up until now, [getkc id="74" comment="Moore's Law"] provided an easy path to enable this. By adopting each smaller node, transistors were cheaper, but that is no longer the case, as explained in a recent article. The industry will need to find new technologies to make this happen and some people are looking towards... » read more

Manufacturing Bits: June 24
By Mark LaPedus - 24 Jun, 2014 - Comments: 0

A cup of sub-wavelength images The National Institute of Standards and Technology (NIST) and the University of Michigan have developed a technology that could enable sub-wavelength images at radio frequencies. Researchers used a mere glass cup, and laser light at optical wavelengths, to measure and image RF fields. In the future, this technology could measure the behavior of metamaterials. ... » read more

Executive Insight: CH Wu
By Ed Sperling - 21 Apr, 2014 - Comments: 0

Semiconductor Engineering sat down with CH Wu, president and CEO of Advantest Taiwan, to talk about business, politics, and his philosophy on what really motivates people. What follows are excerpts of that conversation. SE: Tell us a little about who you are and your background. Wu: I graduated from college with a degree in electrical engineering and started at Philips Electric, then moved ... » read more

Time To Revisit 2.5D And 3D
By Mark LaPedus - 17 Apr, 2014 - Comments: 2

Chipmakers are reaching various and challenging inflection points. In logic, many IC makers face a daunting transition from planar transistors at 20nm to finFETs at 14nm. And on another front, the industry is nearing the memory bandwidth wall. So perhaps it’s time to look at new alternatives. In fact, chipmakers are taking a hard look, or re-examining, one alternative—stacked 2.5D/3D chi... » read more

Challenges In 3D Resists
By Katherine Derbyshire - 24 Mar, 2014 - Comments: 2

3D integration straddles the line between CMOS fabs and packaging and assembly houses. Depending on the structure being fabricated, the most appropriate process might be more “CMOS-like” or more “package-like.” For example, in CMOS fabs lithography means spin-on photoresist, exposed by a high precision stepper. Inherent in this approach is an assumption that the wafer surface is flat... » read more

Many Stresses Impact TSVs
By Ann Mutschler - 20 Feb, 2014 - Comments: 0

Too much stress in humans is typically not beneficial, and the same goes for 3D-ICs with through-silicon vias (TSVs). Stress effects here come from the fact that copper, which is the conductor of choice for the TSVs, and silicon have different coefficients of thermal expansion. “If you can imagine that a via will be etched through the silicon, copper will be deposited inside and then t... » read more

Heat Problems Grow With FinFETs, 3D-ICs
By Ann Mutschler - 13 Feb, 2014 - Comments: 2

From high-end consumer devices to rack-mounted arrays inside of data centers, thermal issues are becoming more serious—and getting much more attention. Driving this shift is the move from single chips to 3D ICs, whether they are interposer-based or stacked die. It’s a well-understood challenge: Die stacking can cause thermal issues because of the lack of a readily accessible thermal diss... » read more

Manufacturing Bits: Jan. 21
By Mark LaPedus - 21 Jan, 2014 - Comments: 1

Redefining The Kilogram In 2011, the General Conference on Weights and Measures approved a plan to redefine the kilogram and other measurement units. The new definition for the kilogram will be based on the fixed numerical values of Planck’s constant (h), according to the National Institute of Standards and Technology (NIST), part of the U.S. Department of Commerce. NIST has taken steps t... » read more

Momentum Builds For Monolithic 3D ICs
By Mark LaPedus - 14 Nov, 2013 - Comments: 1

The 2.5D/3D chip market is heating up on several fronts. On one front, stacked-die using through-silicon vias (TSVs) is taking root. In a separate area, Samsung is sampling the world’s first 3D NAND device, with Micron and SK Hynix expected to follow suit. And now, there is another technology generating steam—monolithic 3D integrated circuits. In stacked-die, bare die are connected using... » read more

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