tag: test

Testing Against Changing Standards In Automotive
By Ed Sperling and Kevin Fogarty - 08 Oct, 2019 - Comments: 0

The infusion of more semiconductor content into cars is raising the bar on reliability and changing the way chips are designed, verified and tested, but it also is raising a lot of questions about whether companies are on the right track at any point in time. Concerns about liability are rampant with autonomous and assisted driving, so standards are being rolled out well in advance of the te... » read more

Advanced Features Of High-Speed Digital I/O Devices: Data Delay
By NI - 07 Oct, 2019 - Comments: 0

In high speed digital communications, because of factors such as setup time and hold time, it might be important to delay the data from the edge of the clock. The different settings and parameters that affect data delay are discussed in this white paper. To read more, click here. » read more

Hierarchical DFT: Proven Divide-And-Conquer Solution Accelerates DFT Implementation And Reduces Test Costs
By Mentor, a Siemens Business - 07 Oct, 2019 - Comments: 0

Implementation of the most challenging DFT tasks is greatly simplified by the proven and widely-adopted automation available in Tessent products. This whitepaper describes the basic components of an RTL-based hierarchical DFT methodology, the benefits that it provides, and the tool automation that is available through Mentor’s Tessent products. The focus is on the techniques and automation of... » read more

New Challenges In Testing 5G Devices
By Ed Sperling - 07 Oct, 2019 - Comments: 0

Alejandro Buritica, senior solutions marketing manager at National Instruments, talks about what will be needed for mass-market testing of 5G devices, how to focus signals to overcome signal attenuation, and how to make over-the-air testing viable where leads are not exposed. » read more

The Growing Impact Of Portable Stimulus
By Brian Bailey - 26 Sep, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Dave Kelf, chief marketing officer for Breker Verification Systems; Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemen... » read more

Scan Compression Is No Longer About Compression
By Rohit Kapur - 16 Sep, 2019 - Comments: 0

Scan compression was introduced in the year 2000 and has seen rapid adoption. Nearly every design’s test methodology today implements this technology, which inserts compression logic in the scan path between the scan I/Os and the internal chains. In this article, we take a critical look at the technology to understand how scan compression has matured. The road to scan compression Since th... » read more

Test On New Technology’s Frontiers
By Ed Sperling And Susan Rambo - 10 Sep, 2019 - Comments: 2

Semiconductor testing is getting more complicated, more time-consuming, and increasingly it requires new approaches that have not been fully proven because the technologies they are addressing are so new. Several significant shifts are underway that make achieving full test coverage much more difficult and confidence in the outcome less certain. Among them: Devices are more connected an... » read more

The Hidden Potential Of Test Engineers
By Marie Ryan - 10 Sep, 2019 - Comments: 0

Design engineers are seen as the cornerstone of new projects in many semiconductor companies, working away with the team to design the next product and making sure it meets all specifications. We pay little thought to the test engineer, who works in the shadows designing algorithms, hardware and software that could pass or fail each die. The test engineer is the last line of defense between... » read more

Highly Efficient Scan Diagnosis With Dynamic Partitioning
By Jayant D'Souza - 10 Sep, 2019 - Comments: 0

Charged with the task of improving yield, product engineers need to find the location of defects in manufactured ICs quickly and efficiently. Typically, they use volume scan diagnosis to generate large amounts of data from failing test cycles, which is then analyzed to reveal the location of defects. Scan failure data provides the basis for many decisions in the failure analysis and yield impro... » read more

Improve Volume Scan Diagnosis Throughput 10X With Dynamic Partitioning
By Mentor, a Siemens Business - 09 Sep, 2019 - Comments: 0

Performing volume scan diagnosis on today’s large, advanced node designs puts demands on turn-around-time and compute resources. This paper describes a new technique to maximize diagnosis throughput while performing ever more demanding scan diagnosis. The dynamic partitioning technology in Tessent Diagnosis enables in a 50% reduction in scan diagnosis time using only 20% of the typical memory... » read more

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