Bridging The Gap Between RF Front-End Module Characterization And Production Test With The Semiconductor Test System

By NI - 17 Aug, 2016 - Comments: 0

The rapid evolution of wireless connectivity has driven continual consumer thirst for more data throughput and reduced time to market. These pressures have led to modern signaling standards such as 802.11ac and LTE-Advanced, which have placed even more challenging design and test requirements on the most nonlinear and energy-demanding component in the transmitter, the RF power amplifier. The in... » read more

Connected Reliability Concerns

By Ed Sperling - 04 Aug, 2016 - Comments: 0

Ever since the invention of the integrated circuit, the focus has been on improving technology—making it faster, smaller, cheaper, while also cutting the power budget. With the advent of the IoT and ubiquitous connectivity, the value proposition will change. Rather than just improving the chip, the focus will shift to how that chip behaves in context. How does it work in a connected world... » read more

Gaps Emerge In Test Flows

By Ed Sperling - 04 Aug, 2016 - Comments: 0

Gaps are showing up in test flows as chipmakers add more analog content and push into more safety-critical applications, exposing more points at which designs need to be tested as well as weaknesses in current tools and methodologies. The cornerstone of the [getkc id="76" kc_name="IoT"], and connected devices such as self-driving cars, is a heavy reliance on [getkc id="187" kc_name="sensors"... » read more

Executive Insight: Jack Harding

By Ed Sperling - 03 Aug, 2016 - Comments: 0

[getperson id="11145" comment="Jack Harding"], president and CEO of [getentity id="22242" e_name="eSilicon"], sat down with Semiconductor Engineering to talk about consolidation, business relationships, what it will take to survive in the IoT age, and how to better optimize chips. What follows are excerpts of that conversation. SE: We’ve been looking at consolidation for a while and all th... » read more

ISO 26262-Certified Solution For Testing of Safety-Critical Automotive ICs

By Synopsys - 29 Jun, 2016 - Comments: 0

Anti-lock braking systems, air bags, traction control, and electronic stability control are just a few examples of typical safety systems in current production cars. Next-generation safety systems, known as Advanced Driver Assistance Systems, or ADAS, are setting up the path for semi- and fully autonomous cars of the near future. Some ADAS technology uses a combination of cameras and radar to s... » read more

A New Approach For IC Test

By NI - 22 Jun, 2016 - Comments: 0

Since its inception, a founding principle of the semiconductor industry has been to continually improve performance while driving down cost. In other words, offer more for the money. However, amid greater device complexity, shorter product cycles, and relentless cost pressure, the test portion represents an increasing percentage of the total IC cost and a significant part of the product develop... » read more

The Trouble With MEMS

By Ed Sperling - 25 May, 2016 - Comments: 0

The advent of the Internet of Things will open up a slew of new opportunities for MEMS-based sensors, but chipmakers are proceeding cautiously. There are a number of reasons for that restraint. Microelectromechanical systems are difficult to design, manufacture and test, which initially fueled optimism in the MEMS ecosystem that this market would command the same kinds of premiums that analo... » read more

Highly Parallel Wafer Level Reliability Systems With PXI SMUs

By NI - 18 May, 2016 - Comments: 1

Reliability testing has long served as a method of ensuring that semiconductor devices maintain their desired performance over a given lifetime. As IC manufacturers continue to introduce new and innovative processes with decreasing device geometries, they need to ensure the additional complexity from these changes does not affect the long-term reliability of their ICs. Additionally, major techn... » read more

Accelerating Design-For-Test Pattern Simulation

By Mentor, a Siemens Business - 23 Mar, 2016 - Comments: 0

The Veloce DFT App presents a true “left shift” improvement for a traditional chip design schedule that requires comprehensive gate-level simulations to develop ATPG, BIST, or functional patterns. It enables running complete patterns for DFT verification in a reasonable time to shorten the pattern development cycle. The Veloce DFT App fits seamlessly into the Veloce ecosystem, enabling a ho... » read more

Automotive Semiconductor Test

By Mentor, a Siemens Business - 16 Mar, 2016 - Comments: 0

We are witnessing the gradual transition of the automobile from a simple means of transportation to a mobile electronic hub. The amount of electronic content in passenger cars continues to grow rapidly. Recent reports indicate that electronics now contribute about 40% of the total costs of a traditional, internal combustion engine car, and this jumps as high as 75% for the growing number of ele... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?