The Week In Review: Aug. 12

By Ed Sperling - 12 Aug, 2013 - Comments: 0

By Mark LaPedus Is the sky falling on semi capital spending? “We have seen several 2014 industry demand estimates in the 20%+ range, based on the ramps of FinFET and 3D NAND,” said Weston Twigg, an analyst with Pacific Crest Securities. “We expect Samsung to ramp spending in Q4, but we believe foundry and logic spending will remain soft for several quarters. As a result, we are developin... » read more

Software Debug Gets Tricky

By Ann Mutschler - 11 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler As designs continue to grow in size and complexity, that complexity has led to an increasing number of processing cores. Additional cores, in turn, allow for additional software to be run on those cores, and debugging the software becomes critical. Traditionally, emulation has played a significant role in verifying that software against RTL code, and continues to d... » read more

The Week In Review: June 21

By Ed Sperling - 21 Jun, 2013 - Comments: 0

By Ed Sperling Mentor Graphics rolled out emulation-ready verification IP for MIPI camera and display-based protocols. The VIP enables stimuli generated by UVM and SystemC-based environments and applies them to a design under test (DUT) running in the emulator. Synopsys introduced a tool for implementing and verifying functional engineering change orders, including matching, visualization ... » read more

Managing Functional Verification Projects

By Various Writers - 31 Jan, 2013 - Comments: 0

The adoption of advanced verification languages and methodologies requires evolution of project management techniques in addition to the change in engineering practices. Managers must be able to assess and manage key project elements such as team expertise, verification methodology, verification IP (VIP) selection and environment setup to successfully deploy high-level verification environments... » read more

VIP: Behind The Velvet Rope

By Ed Sperling - 20 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler Some years ago, as engineering teams began to incorporate more protocols into designs and as those protocols grew in sophistication and complexity in order to deliver additional performance, the verification task grew concurrently. At the same time, the design IP market was growing as complexity drove re-use of components, along with verification components—most com... » read more

Exclusive Research: What’s Happening With Third-Party IP

By Ed Sperling - 27 Mar, 2009 - Comments: 0

Analog and mixed signal IP began closing the gap with digital core IP in design explorations in the first two months of this year, a clear sign that multicore systems on chip have emerged as the dominant semiconductor model and that the architecture requires both types of IP. While it’s too early to tell this year what effect that will have on overall design activity—the economy is the rea... » read more

Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

Defining The Chiplet Socket

The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?

by Brian Bailey

tag: verification IP

The Week In Review: Aug. 12

Software Debug Gets Tricky

The Week In Review: June 21

Managing Functional Verification Projects

VIP: Behind The Velvet Rope

Exclusive Research: What’s Happening With Third-Party IP

Trending Articles

NAND Flash Targets 1,000 Layers

Testing For Thermal Issues Becomes More Difficult

Auto Chip Aging Accelerates In Hot Climates

Is In-Memory Compute Still Alive?

Top-Down Vs. Bottom-Up Chiplet Design

Knowledge Centers
Entities, people and technologies explored