tag: Accellera

Using FPGAs For Emulation
By Krzysztof Szczur - 30 Nov, 2017 - Comments: 0

For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather than capabilities they were called “Big Box” emulators and typically were used in order to recover some of the time lost on RTL simulation. Meanwhile, FPGA technology has been available long enough to mature to the point where FPGA bas... » read more

Three Things You Need To Know To Use The Accellera PSS
By Cadence - 29 Nov, 2017 - Comments: 0

Three primary considerations for adopting the Accellera Portable Stimulus Standard (PSS) are understanding the following: the value and relevance of this standard; the fundamental concepts of PSS modeling, including building blocks, process, and mindset; and PSS portability and how these scenarios can be applied to a specific platform. In this paper, we explore these three topics. To read mo... » read more

An Incremental Approach To Reusing Automated Tests From IPs To SoCs
By Matthew Ballance - 09 Nov, 2017 - Comments: 0

Over the past few years, lots of energy has been invested in improving the productivity and quality-of-results of design verification. A promising effort toward this end is that both commercial and in-house tools have been developed to improve the productivity and efficiency of verification at the block, subsystem, and system levels. These tools raise the level of abstraction, increase test-gen... » read more

Automating Tests With Portable Stimulus From IP To SoC Level
By Mentor, a Siemens Business - 08 Nov, 2017 - Comments: 0

The aim of the Portable Stimulus Working Group is to make the creation of highly-efficient automated tests portable. Portable stimulus tools help to raise the level of test description and enable modeling of scenarios that would be very challenging to create with directed and transaction-level constrained random tests. This paper describes the goals of the portable stimulus specification as wel... » read more

The Week In Review: Design
By Jesse Allen - 20 Oct, 2017 - Comments: 0

M&A Synopsys acquired Sidense, a provider of antifuse one-time programmable (OTP) non-volatile memory (NVM) for standard-logic CMOS processes. Sidense was founded in 2004 in Canada. Terms of the deal were not disclosed. ArterisIP acquired the software and intellectual property rights of iNoCs, a provider of network-on-chip IP and design tools. Founded in 2007, the Swiss company was spun... » read more

Getting A Standard Right The First Time
By Brian Bailey - 02 Oct, 2017 - Comments: 3

The development of standards is a tricky balance, especially when going into areas that are nascent. The [getentity id="22863" e_name="Portable Stimulus Standard"] (PSS), being developed within [getentity id="22028" e_name="Accellera"] is one of those. This could be the most important standard since [gettech id="31017" comment="Verilog"] and [gettech id="31040" comment="VHDL"]. And if there ... » read more

Prototypes Proliferate
By Brian Bailey - 02 Oct, 2017 - Comments: 0

Hardware prototyping and [getkc id="30" kc_name="emulation"] have been two sides of the same coin ever since the [gettech id="31071" comment="FPGA"] became a commercial success. Early emulators were all built from FPGAs, and most were used in-circuit, much like prototypes are today. More recently, emulation has become a major piece of the [getkc id="10" kc_name="verification"] flow, to the poin... » read more

The Week In Review: Design
By Jesse Allen - 29 Sep, 2017 - Comments: 0

M&A Imagination will sell its MIPS business to Tallwood, a California-based venture capital firm, for $65m in cash. The sale is expected to close in October. The rest of Imagination is slated to be sold to Canyon Bridge for £550 million in cash (~$740 million), a deal dependent on the MIPS sale. The Chinese-backed investment firm has featured recently in the news for its attempted purchas... » read more

System Coverage Undefined
By Brian Bailey - 28 Sep, 2017 - Comments: 1

When is a design ready to be taped out? That has been one of the toughest questions to confront every design team, and it's the one verification engineers lose sleep over. Exhaustive [getkc id="56" kc_name="coverage"] has not been possible since the 1980s. Several metrics and methodologies have been defined to help answer the question and to raise confidence that important aspects of a block... » read more

DVCon Europe Takes Over Munich October 16-17
By McKenzie Ross - 28 Sep, 2017 - Comments: 0

DVCon Europe is on the horizon, and this year's program should prove to be very timely. Chips and systems are getting more complex, verification is becoming more difficult, and formal has emerged as a critical piece of the verification suite The lineup this year tackles some key issues facing a changing semiconductor landscape. During a Monday tutorial, “Next Generation ISO 26262-based De... » read more

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