The Week In Review: Design

Synopsys buys OTP NVM maker Sidense; ArterisIP buys iNoCs assets; custom eFPGA blocks; new SystemC library; funding for analog reuse.


Synopsys acquired Sidense, a provider of antifuse one-time programmable (OTP) non-volatile memory (NVM) for standard-logic CMOS processes. Sidense was founded in 2004 in Canada. Terms of the deal were not disclosed.

ArterisIP acquired the software and intellectual property rights of iNoCs, a provider of network-on-chip IP and design tools. Founded in 2007, the Swiss company was spun out of research from EPFL, Stanford, and the University of Bologna and pioneered the field of topology synthesis for the then emerging NoC interconnect IP market. Terms were not disclosed.

Achronix announced it will create optimized, custom blocks for its eFPGA IP customers. The blocks harden repeated functions that are performance and/or area bottlenecks.

Rambus validated interoperability of the Rambus DDR4 PHY and the Arm CoreLink DMC-620 Dynamic Memory Controller. Targeted at Arm-based data centers, the two IP blocks offer up to 3200 Mbps.

Corigine released USB 3.1 Gen 2 PC host and device controller IP. The IP is compliant with USB SuperSpeed+ and has been certified by USB-IF. A 3.1 Gen 2 PHY from M31 Technology was also certified in 28nm.

Allegro DVT uncorked new encoder IPs. The AL-E110 encoder IP has a new cache architecture for a smaller area, targets high-end video applications and supports H.264/AVC, H.265/HEVC and VP9 video formats and JPEG still images. A lightweight version is also available.

DENSO licensed Arm’s Cortex-R52 processor for use in its reference platforms for automated driving systems and vehicle control.

Hiroshima University adopted Cadence’s Vision P6 DSP for convolutional neural network (CNN) processing and support vector machine (SVM) classification in its development of a computer-aided diagnosis system for colorectal endoscopic images. The system was verified on Cadence’s FPGA prototyping platform.

Accellera published a new library release for the SystemC core language. The SystemC 2.3.2 proof of concept library adds modern C++ support, an extended hierarchical name registry, a new common base class for TLM-2.0 sockets, new conversion functions of time values from and to strings, and a reworked build system supporting additional compilers and platforms. The new library is fully compatible with IEEE Std. 1666-2011 and is available through the IEEE Get Program.

The public review period for the Portable Stimulus Specification has been extended to Oct. 30. The specification defines a standard mechanism for the specification of verification intent and behaviors that would be reusable across target platforms and allow for the automation of test generation through a new Domain Specific language and equivalent C++ Class Library. The Early Adopter release is available from Accellera.

Thalia Design Automation completed a $865k (£640k) funding round, led by existing investors Mercia Fund Managers and Finance Wales. Founded in 2011, Thalia provides tools for analog IP reuse, design migration and derivative creation, and will use the funds to expand its customer base and hire more analog IC developers.

Market research firm IC Insights raised its 2017 IC market growth rate forecast to 22%, due to the boom in the DRAM and NAND flash markets. The firm expects a massive 77% increase in DRAM ASP this year, driving the DRAM market to 74% growth for 2017. The total memory market is forecast to jump by 58% in 2017 with another 11% increase forecast for 2018. Excluding DRAM and NAND, the IC industry is forecast to grow by 9%.

Dr. Rob A. Rutenbar, senior vice chancellor for Research at the University of Pittsburgh, was awarded the 2017 Phil Kaufman Award for his contributions to algorithms and tools for analog and mixed-signal designs. He also co-founded Neolinear, an analog tool company acquired by Cadence.

eSilicon launched a six-month intensive training course focused on finFET ASIC design, test, verification, and packaging in Bucharest, Romania. It is open to university final-year students and graduates.

Arm TechCon: Oct. 24-26 in Santa Clara, CA. The Arm ecosystem-focused conference features a number of keynotes from Arm on subjects from the value of IoT data to state-of-the-art silicon process technologies. Invited speakers Stacey Higginbotham, Mary Aiken, and Jessica Barker will discuss the key challenges facing IoT and why a more human-centered approach is needed when designing security.

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