Starting Point Is Changing For Designs

By Ed Sperling - 04 Oct, 2017 - Comments: 0

The starting point for semiconductor designs is shifting. What used to be a fairly straightforward exercise of choosing a processor based on power or performance, followed by how much on-chip versus off-chip memory is required, has become much more complicated. This is partly due to an emphasis on application-specific hardware and software solutions for markets that either never existed befo... » read more

A Chip For All Seasons

By Jeff Dorsch - 07 Sep, 2017 - Comments: 0

FPGAs are showing up in more designs and in more markets, and as they get included in more systems they are becoming much more complex. A decade ago, the key markets for [gettech id="31071" t_name="FPGAs"] were industrial, medical, automotive and aerospace. Those markets remain strong, but FPGAs also are playing a role in artificial intelligence, data centers, the [getkc id="76" kc_name="... » read more

Tech Talk: eFPGA Test

By Ed Sperling - 07 Sep, 2017 - Comments: 0

Volkan Oktem, director of product applications at Achronix, explains how to design a test approach for embedded FPGAs, including how to plan for sufficient coverage and how much it will cost. https://youtu.be/aGXd8QH-BfY Related Stories Tech Talk: EFPGA Acceleration When and why to use embedded FPGAs. » read more

The Limits Of IP Reuse

By Ed Sperling - 07 Sep, 2017 - Comments: 0

The basic business proposition for third-party IP is that it's cheaper, faster, and less problematic to buy rather than build. But things haven't exactly worked out according to plan, either for companies that license IP or those that develop it. For [getkc id="43" kc_name="IP"] licensees, just keeping track of an endless series of updates is becoming unwieldy. Complex designs often include ... » read more

Embedded FPGA Acceleration In SoCs

By Achronix - 06 Sep, 2017 - Comments: 0

The Speedcore design and integration methodology has been defined with intimate awareness of the difficulties ASIC engineering teams must contend with. All the necessary files and flows for capturing the functional, timing and power characteristics of a user-defined and programmed Speedcore instance, along with support for successfully reconfiguring an already field-deployed Speedcore IP embedd... » read more

How To Close Timing With An eFPGA Hosted In An SoC

By Volkan Oktem - 03 Aug, 2017 - Comments: 0

eFPGAs are embeddable IP that include look-up tables, memories, and DSP building blocks, allowing designers to add a programmable logic fabric to their SoC. The Speedcore IP can be configured to any size as dictated by the end application. The SoC supplier defines the number of LUTs, memory resources, and DSP64 blocks for their Speedcore instance. A short time later, Achronix delivers the IP as... » read more

CCIX Enables Machine Learning

By Brian Bailey - 31 Jul, 2017 - Comments: 5

It takes a lot of technology to enable something like machine learning, and not all of it is as glamorous as neural network architectures and algorithms. Several levels below that is the actual hardware on which these run, and that brings us into the even less sexy world of interfaces. One such interface, the Cache Coherent Interconnect for Accelerators (CCIX), pronounced C6, aims to make th... » read more

The Secret Life Of Accelerators

By Ed Sperling - 27 Jul, 2017 - Comments: 0

Accelerator chips increasingly are providing the performance boost that device scaling once provided, changing basic assumptions about how data moves within an electronic system and where it should be processed. To the outside world, little appears to have changed. But beneath the glossy exterior, and almost always hidden from view, accelerator chips are becoming an integral part of most des... » read more

What Does An IoT Chip Look Like?

By Ed Sperling - 19 Jul, 2017 - Comments: 4

By Ed Sperling and Jeff Dorsch Internet of Things chip design sounds like a simple topic on the face of it. Look deeper, though, and it becomes clear there is no single IoT, and certainly no type of chip that will work across the ever-expanding number of applications and markets that collectively make up the IoT. Included under this umbrella term are sensors, various types of processors, ... » read more

The Week In Review: Design

By Jesse Allen - 16 Jun, 2017 - Comments: 0

M&A Verific acquired Invionics' entire INVIO technology portfolio, adding a high-level scripting interface with 100 high-level APIs to its Parser Platform of approximately 2,000 low-level SystemVerilog and VHDL APIs. An R&D group from the company will also join Verific. Portable Stimulus An Early Adopter release of the Portable Stimulus specification has been made publicly availabl... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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