Week In Review: Manufacturing, Test

By Mark LaPedus - 02 Nov, 2018 - Comments: 0

Chipmakers A U.S. federal grand jury has indicted Chinese DRAM maker Jinhua Integrated Circuit Co. (JHICC), Taiwan's UMC and three individuals, charging them with alleged crimes related to a conspiracy to steal, convey, and possess stolen trade secrets from Micron Technology for the benefit of a company controlled by the China government. In addition, the U.S. filed a civil lawsuit seeking... » read more

AI Begins To Reshape Chip Design

By Ed Sperling - 01 Nov, 2018 - Comments: 1

Artificial intelligence is beginning to impact semiconductor design as architects begin leveraging its capabilities to improve performance and reduce power, setting the stage for a number of foundational shifts in how chips are developed, manufactured and updated in the future. AI—and machine learning and deep learning subsets—can be used to greatly improve the functional control and pow... » read more

A Crisis In DoD’s Trusted Foundry Program?

By Mark LaPedus - 22 Oct, 2018 - Comments: 0

The U.S. Department of Defense’s Trusted Foundry program is in flux due to GlobalFoundries’ recent decision to put 7nm on hold, raising national security concerns across the U.S. defense community. U.S. DoD and military/aerospace chip customers currently have access to U.S.-based “secure” foundry capacity down to 14nm, but that's where it ends. No other foundries provide similar “s... » read more

eFPGA vs. FPGA Design Methodologies

By Ed Sperling - 05 Oct, 2018 - Comments: 0

Namit Varma, senior director of Achronix’s India Technology Center, discusses the differences between discrete and embedded FPGAs. https://youtu.be/Vwo3ktQvcKc » read more

Making Buildings Smarter

By Jeff Dorsch - 04 Oct, 2018 - Comments: 1

Calling a building “smart” implies that technology is embedded to make that building more efficient, useful, convenient and profitable. The goal is to program efficiency beyond what humans can provide. But “smart” also may imply a healthy dose of marketing hype. No one wants to live in a “dumb building,” but it's difficult to define what makes a building smart. And while much is ... » read more

Achieving eFPGA Timing Closure In An ASIC

By Alok Sanghavi - 04 Oct, 2018 - Comments: 0

When we start school as young children, one of the first lessons we learn is how to share, followed quickly by not running with scissors. As Kent Orthner, Achronix’s senior director of Systems Engineering, discussed at the Design Automation Conference in June, sharing is also key when it comes to closing timing with embedded FPGAs (eFPGAs). With an eFPGA, such as Achronix’s Speedcore IP,... » read more

Machine Learning Shifts More Work to FPGAs, SoCs

By Kevin Fogarty - 24 Sep, 2018 - Comments: 0

A wave of machine-learning-optimized chips is expected to begin shipping in the next few months, but it will take time before data centers decide whether these new accelerators are worth adopting and whether they actually live up to claims of big gains in performance. There are numerous reports that silicon custom-designed for machine learning will deliver 100X the performance of current opt... » read more

Deriving Configuration Time For eFPGAs

By Volkan Oktem - 06 Sep, 2018 - Comments: 0

Part 1 of this blog post described how to configure an eFPGA, using Achronix’s Speedcore eFPGA as an example. It explained why each instance of the eFPGA in an ASIC or SoC design must be configured after the system powers up due to its nonvolatile SRAM technology to store configuration bits. This post will detail how the configuration time is derived, once again using Speedcore eFPGA as th... » read more

Achieving ASIC Timing Closure With Speedcore eFPGAs

By Achronix - 05 Sep, 2018 - Comments: 0

Achronix's Speedcore eFPGA IP allows companies to embed a programmable logic fabric in their ASICs, delivering to end users the capability to modify or upgrade the functionality of an ASIC after being deployed in the field. This flexibility dramatically expands the solution space that can be served by the ASIC as it can be updated to support changing standards and algorithms. Timing closure is ... » read more

Partitioning Drives Architectural Considerations

By Ann Mutschler - 29 Aug, 2018 - Comments: 0

There are multiple reasons for design partitioning. One is complexity, because it’s faster and simpler to divide and conquer, particularly with third-party IP. A second reason involves power, where it may be more efficient to divide up functionality so each function be right-sized. A third involves performance, where memory utilization and processing can be split up according to functional pr... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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